Patents by Inventor Lynda C. Mantalas
Lynda C. Mantalas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7655482Abstract: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.Type: GrantFiled: January 9, 2007Date of Patent: February 2, 2010Assignee: KLA-TencorInventors: Akella V. S. Satya, Lynda C. Mantalas, Gustavo A. Pinto
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Publication number: 20080246030Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.Type: ApplicationFiled: February 14, 2007Publication date: October 9, 2008Inventors: Akella V.S. Satya, Gustavo A. Pinto, David L. Adler, Robert Thomas Long, Neil Richardson, Kurt H. Weiner, David J. Walker, Lynda C. Mantalas, Padma A. Satya
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Patent number: 7179661Abstract: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.Type: GrantFiled: August 25, 2000Date of Patent: February 20, 2007Assignee: KLA-TencorInventors: Akella V. S. Satya, Lynda C. Mantalas, Gustavo A. Pinto
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Patent number: 6921672Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.Type: GrantFiled: January 7, 2003Date of Patent: July 26, 2005Assignee: KLA-Tencor Technologies CorporationInventors: Akella V. S. Satya, Gustavo A. Pinto, David L. Adler, Robert Thomas Long, Neil Richardson, Kurt H. Weiner, David J. Walker, Lynda C. Mantalas
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Patent number: 6576923Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.Type: GrantFiled: June 21, 2002Date of Patent: June 10, 2003Assignee: KLA-Tencor CorporationInventors: Akella V. S. Satya, Robert Thomas Long, Lynda C. Mantalas, Gustavo A. Pinto, Neil Richardson
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Publication number: 20030096436Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.Type: ApplicationFiled: January 7, 2003Publication date: May 22, 2003Applicant: KLA-Tencor Technologies CorporationInventors: Akella V. S. Satya, Gustavo A. Pinto, David L. Adler, Robert Thomas Long, Neil Richardson, Kurt H. Weiner, David J. Walker, Lynda C. Mantalas
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Patent number: 6528818Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.Type: GrantFiled: August 25, 2000Date of Patent: March 4, 2003Assignee: KLA-TencorInventors: Akella V. S. Satya, Gustavo A. Pinto, David L. Adler, Robert Thomas Long, Neil Richardson, Kurt H. Weiner, David J. Walker, Lynda C. Mantalas
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Patent number: 6509197Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.Type: GrantFiled: August 25, 2000Date of Patent: January 21, 2003Assignee: KLA-Tencor CorporationInventors: Akella V. S. Satya, Robert Thomas Long, Lynda C. Mantalas, Gustavo A. Pinto, Neil Richardson
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Publication number: 20020187582Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.Type: ApplicationFiled: June 21, 2002Publication date: December 12, 2002Applicant: KLA-Tencor CorporationInventors: Akella V. S. Satya, Robert Thomas Long, Lynda C. Mantalas, Gustavo A. Pinto, Neil Richardson