Abstract: Apparatus and article of manufacture for disabling on-demand access to computerized resources on a computerized apparatus are disclosed. The method comprises receiving a disablement code; validating the disablement code; and disabling an on-demand resource if the validating is successful, thereby rendering the disabled on-demand resource unavailable for use by users of the computerized apparatus, wherein the disabled on-demand resource is a hardware resource of the computerized apparatus. Another embodiment includes receiving a disablement code comprising encrypted data, validating the disablement code, disabling at least one on-demand resource if the validating is successful.

Abstract: Apparatus and article of manufacture for disabling on-demand access to computerized resources on a computerized apparatus are disclosed. The method comprises receiving a disablement code; validating the disablement code; and disabling an on-demand resource if the validating is successful, thereby rendering the disabled on-demand resource unavailable for use by users of the computerized apparatus, wherein the disabled on-demand resource is a hardware resource of the computerized apparatus. Another embodiment includes receiving a disablement code comprising encrypted data, validating the disablement code, disabling at least one on-demand resource if the validating is successful.

Abstract: Method, apparatus and article of manufacture for disabling on-demand access to computerized resources on a computerized apparatus. The method comprises receiving a disablement code; validating the disablement code; and disabling an on-demand resource if the validating is successful, thereby rendering the disabled on-demand resource unavailable for use by users of the computerized apparatus, wherein the disabled on-demand resource is a hardware resource of the computerized apparatus. Another embodiment includes receiving a disablement code comprising encrypted data, validating the disablement code, disabling at least one on-demand resource if the validating is successful. The validating includes generating a first key using system information unique to the computerized apparatus; decrypting the encrypted data using a second key to produce decrypted data; encrypting a value to produce an encrypted value; decrypting the encrypted value to produce a decrypted value; and comparing the value to the decrypted value.

Abstract: An information processing network includes multiple processing devices, a main storage memory, one or more disk drives or other auxiliary storage devices, and an interface for coupling the processing devices to the main storage memory and the auxiliary devices. A primary directory in main storage contains mapping information for translating virtual addresses to real addresses in main storage. Look-aside buffers in the processing devices duplicate some of the mapping information. A primary directory hardware lock, subject to exclusive control by any one of the processing devices to update the primary directory, inhibits access to the primary directory based on hardware address translations initiated when one of the processors holds the primary directory lock. Address translations in progress when the lock is acquired proceed to completion before the primary directory is updated under the lock. Accordingly, such updates proceed atomically relative to hardware primary directory searches.

Abstract: A computer program synchronization instruction is employed to synchronize multiple processing devices sharing main storage through a common interface. The processors execute the synchronization instruction in turn, and all except the final processor are forced into a temporary holdoff condition and execute no further computer program instructions. The final processor to execute the synchronization program becomes a master, releasing itself and the "slave" devices simultaneously to resume executing instructions. In order to force contentions between processors, a selected delay may be entered into the instruction stream of at least one of the processing devices. The delay can be incremented each time the synchronization instruction is executed, if desired. The forced contentions permit a testing of various serialization mechanisms designed to resolve contentions.

Abstract: In connection with an information processing network in which multiple processing devices have individual cache memories and also share a main storage memory, a process is disclosed for allocating multiple data operations or tasks for subsequent execution by the processing devices. A plurality of task dispatching elements (TDE) forming a task dispatching queue are scanned in an order of descending priority, for either a specific affinity to a selected one of the processing devices, or a general affinity to all of the processing devices. TDEs with specific affinity are assigned immediately if the selected processor is available, while TDEs of general affinity are reserved. TDEs with a specific affinity are bypassed if the selected processor is not available, or reserved if a predetermined bypass threshold has been reached. Following the primary scan a secondary scan, in an order of ascending priority, assigns any reserved tasks to the processing devices still available, without regard to processor affinity.

Abstract: A microcode branch, to one of a number of possible control words (sixteen control words are described), is based upon (1) the remaining operand length that is to be processed by a left to right instruction, and (2) by the byte alignment of the portion of the operand that currently resides in main storage interface registers. As a left to right instruction is being executed, the operand's new length and its new alignment, as they both will exist after a control word is executed, are determined. The new length and the new alignment are used to determine the addess of the next control word. A 16-way branch instruction has branch legs that are determined by the number of operand bytes that are left to be processed, and by the alignment of two operands in two storage registers that interface with main storage. This method and arrangement for microcode branching maximizes the amount of data that can be processed per processor cycle by the hardware upon execution of a left to right instruction.

Abstract: A look-aside buffer in a computer system has a memory containing at least a first type of data ans a second type of data stored in a page format. The look-aside buffer is arranged to retain at least two different real addresses as resolved by the system which indicate pages containing the different types of data. One of the addresses is indicated as least recently used by a marker and such address is deleted when a further different address is resolved by the system unless the address being resolved is an address corresponding to the first type of data. In such a case, the marker is not changed such that the second type of data addresses are not deleted from the look-aside buffer as a result of resolution of a first type data page address by the system.