Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

Abstract: A control circuit arrangement for storing the addressability defined by the current active address key (AAK) being accessed in an address key register (AKR) in a processor. This AAK is stored in a last AAK register. When a hard or soft check interrupt occurs, the AAK stored in the last AAK register is designated as the processor's last key saved (i.e. LKSA) to define an interrupted addressability being used by the processor at the time of an interrupt. Upon occurrence of an interrupt, the LSKA represents the interrupted addressability, which is then made available to the processor by gating the LKSA into a source operand key section in the AKR from the processor's last AAK register, and setting the key for a supervisor program into another section of the AKR, so that the supervisor program can take corrective or termination actions. Until the LKSA gating into the AKR is completed, no AAK can be ingated into the last AAK register.

Abstract: Active address keys (AAK) are translated into respective addressabilities in physical main memory. Each addressability comprises one or more physical blocks which may be scattered in the main memory. Each address key represents the assigned addressability in main memory for a logical address space. Plural key register sections may be loaded with the same or different address keys. For each storage access request, received from a processor or I/O channel, AAK select circuits outgate to the translator the key in the key register section corresponding to the type of the current storage access request to determine the addressability available to the access request. Each address key identifies a particular stack of one or more segmentation registers. Each segmentation register can be assigned the address of any segment (i.e. a block of contiguous physical addresses located anywhere in the main memory). Each segmentation register also has validity and read-only flag bits for its assigned block.