Abstract: Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads.

Abstract: Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads.

Abstract: Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads.

Abstract: Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads.

Abstract: Methods and structure for improved design remediation for previously inexplicable damage to core circuits of an application circuit design caused by CDM ESD events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Features and aspects hereof automatically alter an application circuit design to provide remediation by various techniques to reduce the magnitude of such inductive coupling and to thereby reduce susceptibility of the application circuit to damage from CDM ESD events. The modifications may be enforced as rules during initial design of the application circuit or as reconfiguration of a design in response to simulation to discover inappropriate coupling in the design.

Abstract: Methods and structure for improved simulation of CDM ESD events and for remediation of circuit designs correcting for previously inexplicable damage to core circuits of an application circuit design caused by such events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Improved simulation techniques in accordance with features and aspects hereof may predict where such inductive coupling may cause damage to core circuits. Other features and aspects hereof may alter an application circuit design to provide remediation by automated insertion of additional buffer circuitry to core traces of the core circuitry that may be impacted by such inductive coupling.

Abstract: A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.

Abstract: A temperature sensor adapted to produce a temperature-independent voltage and temperature-dependent voltage dependent on an internal control signal, generated within the temperature sensor, adjustable by an adjustment circuit operatively connected to the temperature sensor is provided. The adjustment circuit is controllable to adjust the internal control signal in order to modify an operating characteristic of the temperature sensor.

Abstract: An adjustment and calibration system for post-fabrication treatment of an on-chip temperature sensor is provided. As explained in detail below, the adjustment and calibration system includes at least one adjustment circuit, to which the on-chip temperature sensor is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

Abstract: A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.

Abstract: An adjustment and calibration system for post-fabrication treatment of an on-chip temperature sensor is provided. As explained in detail below, the adjustment and calibration system includes at least one adjustment circuit, to which the on-chip temperature sensor is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

Abstract: A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.

Abstract: A temperature sensor adapted to produce a temperature-independent voltage and temperature-dependent voltage dependent on an internal control signal, generated within the temperature sensor, adjustable by an adjustment circuit operatively connected to the temperature sensor is provided. The adjustment circuit is controllable to adjust the internal control signal in order to modify an operating characteristic of the temperature sensor.

Abstract: A clock grid skew reduction technique that uses one or more biasable delay drivers to compensate for unbalanced loading and/or RC wire delay induced skew is provided. The biasable delay driver has a size that may be varied depending on a delay amount of a signal from a clock source to an input of the biasable delay driver. Depending on the delay amount, the biasable delay driver may be either sized up or sized down to modulate delay in order to reduce or eliminate skew between the clock signal at the input of the biasable delay driver and the clock signal at another point in a circuit.

Abstract: An integrated circuit having a clock driver connected to a non-peripheral region of a clock grid is provided. Providing interconnect that connect a clock driver to non-peripheral regions the clock grid effectively leads to reduced clock skew due to reduced RC delays from clock grid connection points to components operatively connected to the clock grid. Further, a method for reducing clock skew on a clock grid using a wire tree architecture structure is provided.