Abstract: A fault detector processes half cycles of current in variable frequency ac power systems by weighting half cycle magnitude values by the period of the half cycle. Time attenuated accumulations of the weighted half cycle peak values exceeding a first threshold for short delay protection, and of weighted positive differences between the peak values of successive half cycles and the preceding half cycles for a selected period of time after a peak value exceeds a second threshold for arc faults, generate trip signals when they reach specified levels.

Abstract: A fault detector processes half cycles of current in variable frequency ac power systems by weighting half cycle magnitude values by the period of the half cycle. Time attenuated accumulations of the weighted half cycle peak values exceeding a first threshold for short delay protection, and of weighted positive differences between the peak values of successive half cycles and the preceding half cycles for a selected period of time after a peak value exceeds a second threshold for arc faults, generate trip signals when they reach specified levels.

Abstract: Arc faults in ac electric power systems including aircraft 400 Hz and other such ac electrical systems are detected by an arc fault detector generating a time attenuated cumulative sum of amounts by which the current in each most recent cyclic interval of current, preferably each half cycle, exceeds the magnitude of the current in the immediately preceding cyclic interval in absolute magnitude after a first cyclic interval in which the current exceeds a selected arming magnitude. Preferably, the magnitude detected by a peak detector is used, but alternatively differences in the average magnitude or the rms magnitude between half cycles can be accumulated. When the cumulative sum reaches a preset value, an arc fault indication is generated. The time cumulative sum is cleared if it decreases to a preset value and the selected arming current must be exceeded again to reinitiate generation of the time attenuated cumulative sum.

Abstract: A memory alias adapter, coupled to a processor's memory bus, monitors processor memory accesses. Whenever a memory access corresponds to shared memory, rather than memory local to the processor, the adapter constructs a memory request message, and transmits the message over a network link to a shared memory unit. The shared memory unit performs the shared memory access and issues a response message over the network link. The memory alias adapter accepts the response message, and completes processor's memory access on the memory bus. As a result, it is transparent to the processor whether its memory access is to the local memory or to the shared memory.

Abstract: A memory alias adapter, coupled to a processors memory bus, monitors processor memory accesses. Whenever a memory access corresponds to shared memory, rather than memory local to the processor, the adapter constructs a memory request message, and transmits the message over a network link to a shared memory unit. The shared memory unit performs the shared memory access and issues a response message over the network link. The memory alias adapter accepts the response message, and completes processor's memory access on the memory bus.

Abstract: A memory alias adapter, coupled to a processor's memory bus, monitors processor memory accesses. Whenever a memory access corresponds to shared memory, rather than memory local to the processor, the adapter constructs a memory request message, and transmits the message over a network link to a shared memory unit. The shared memory unit performs the shared memory access and issues a response message over the network link. The memory alias adapter accepts the response message, and completes processor's memory access on the memory bus.

Abstract: A memory alias adapter, coupled to a processor's memory bus, monitors processor memory accesses. Whenever a memory access corresponds to shared memory, rather than memory local to the processor, the adapter constructs a memory request message, and transmits the message over a network link to a shared memory unit. The shared memory unit performs the shared memory access and issues a response message over the network link. The memory alias adapter accepts the response message, and completes processor's memory access on the memory bus.

Abstract: A memory alias adapter, coupled to a processor's memory bus, monitors processor memory accesses. Whenever a memory access corresponds to shared memory, rather than memory local to the processor, the adapter constructs a memory request message, and transmits the message over a network link to a shared memory unit. The shared memory unit performs the shared memory access and issues a response message over the network link. The memory alias adapter accepts the response message, and completes processor's memory access on the memory bus. As a result, it is transparent to the processor whether its memory access is to the local memory or to the shared memory.

Abstract: A lubricant composition for treating non-ferrous metals and alloys is provided. In particular, the composition is used to treat metal substrates when the substrates are subjected to various metal working processes. The composition includes an emulsified ester that is combined with non-ferrous lubricating materials. The emulsified ester makes the lubricant water dispersible and therefore easily removable from the metal substrates after treatment. The composition of the present invention is extremely durable, biodegradable and environmentally safe.