Abstract: Techniques for (i) using contextual information associated with an exposed credential to identify a resource that could be accessed using the exposed credential, (ii) identifying a responsible entity of that resource, and (iii) alerting the responsible entity about the exposed credential are disclosed. A credential is determined to be in an exposed state. The exposed credential, if used, could potentially provide an actor access to a resource, despite the fact that the actor should not have access to the resource. The exposed credential is analyzed to determine a context. Based on that context, the resource is identified. A responsible entity associated with the resource is identified. An alert is then sent to that entity.

Abstract: A method for forming an inlaid interconnect structure for ICs. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a dielectric layer and cap layer over the etch stop layer, forming a photoresist pattern, and etching the cap and dielectric to form an opening that is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The dielectric layer and cap layers are then deposited over both regions and two via or trench openings are formed therethrough in the regions, respectively.

Abstract: An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.

Abstract: Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.

Abstract: An interconnect structure is formed with a plurality of layers of a conductive material with a grain boundary between any two adjacent layers of the conductive material. Such grain boundaries between layers of conductive material act as shunt by-pass paths for migration of atoms of the conductive material to minimize migration of atoms of the conductive material along the interface between a dielectric passivation or capping layer and the interconnect structure. When the interconnect structure is a via structure, each of the layers of the conductive material and each of the grain boundary are formed to be perpendicular to a direction of current flow through the via structure. Such grain boundaries formed between the plurality of layers of conductive material in the via structure minimize charge carrier wind-force along the direction of current flow through the via structure to further minimize electromigration failure of the via structure.

Abstract: A method of processing a semiconductor device is disclosed and comprises patterning a multi-layer photoresist which comprises an imaging layer overlying an underlying layer. The patterning of the resist defines an exposed portion of an underlying process layer. The method further comprises inspecting the patterned multi-layer photoresist for defects and re-working the patterned multi-layer photoresist upon a failed inspection. The re-work process comprises depositing a protection layer over the patterned multi-layer photoresist and over the exposed portion of the underlying process layer. A portion of the protection layer and the imaging layer are then removed in a concurrent manner while leaving a remaining portion of the protection layer covering the exposed portion of the underlying process layer. A remaining portion of the protection layer and the underlying layer are then removed in a concurrent manner and such removal does not adversely impact the process layer.

Abstract: A method for forming a metal interconnect comprises exposing a dielectric layer to an etch chemistry containing nitrogen-containing compound such as NH3, NF3 or N2O. The nitrogen-containing compound provides selectivity and/or profile control comparable to that provided by N2, while avoiding poisoning of photoresist by embedded N2.

Abstract: A dual damascene air gap process reduces the dielectric constant, and extends CVD low-k technology by removing the sacrificial intra-metal dielectric between conductive lines by patterned etching and replacement with lower k material. The void space between the narrowly spaced conductive lines is sealed in by the non-conformal CVD deposition, thereby further reducing the overall capacitance of the dual damascene interconnect formation.

Abstract: A method for forming a dual inlaid interconnect structure for ICs is disclosed. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a first dielectric layer, a middle stop layer, a second dielectric layer and a cap layer thereover. The method further comprises patterning the cap, dielectric layers and middle stop layer a via opening down to the etch stop layer that is associated with the opening therein. A trench opening is formed down through the cap and second dielectric layer and stopping on the middle stop layer. The trench/via opening is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer.

Abstract: For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.

Abstract: A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening having side surfaces through the dielectric layer, etching the first barrier layer, and filling the opening with metal to form a first metal feature. The process also includes the step of replacing hydroxyl terminated ions on the side surfaces. This step of replacing the hydroxyl terminated ions can occur after the opening is formed or after the first barrier layer is etched. A semiconductor device produced by the method of manufacturing is also disclosed.

Abstract: In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure through a low temperature conformal CVD process. The polymer layer is anisotropically etched to form spacers on the respective adjacent sidewalls of the photoresist bodies. The substrate is then etched using the spacers as a mask.

Abstract: A method for forming a dual damascene conductive line and conductive plug using porous low k dielectric materials in the via and trench layers. The via layer is provided with dense low k dielectric plugs that increase the mechanical strength of the porous low k dielectric layer that forms the via layer. A via fill technique etches some of the dielectric plugs in the via layer and fills them with conductive material. The via fill technique reduces the damage done to the via holes in the via layer caused by photoresist removal processes.

Abstract: The dimensional accuracy of trench formation and, hence, metal line width, in damascene processing is improved by employing a silicon carbide middle etch stop layer/ARC. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide middle etch stop layer/ARC having an extinction coefficient (k) of about −0.10 to about −0.60.

Abstract: A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the via hole. Once the trench mask has been formed on the CVD organic BARC, the CVD organic BARC may be removed in the same process as the photoresist of the trench mask layer. A properly formed trench will have been created since the via poisoning and resist scumming were substantially eliminated by the presence of the CVD organic BARC.

Abstract: A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening through the dielectric layer, etching the first barrier layer, and filling the opening with metal to form a first metal feature. The first barrier level is etched using CHF3 and CH3F. Additionally, the first barrier layer can be formed from silicon nitride.

Abstract: An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An organic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

Abstract: A composite layer comprising a non-homogenous layer is etched by continuously varying a process parameter, such as the amount of reactive agent in an etchant mixture. Embodiments include etching a silicon oxide film having a varying concentration of carbon through the film with an etchant mixture containing a fluorinated organic, oxygen and an inert gas and continuously increasing and/or decreasing the amount of oxygen in the etchant mixture during etching through the silicon oxide film.

Abstract: Deleterious poisoning of patterned photoresist masking layers accompanying plasma ashing/etching of photoresist and/or low-k dielectric layers in a nitrogen-containing atmosphere is eliminated, or at least substantially reduced, by post-treating exposed surfaces of the low-k dielectric layer(s) with hydrogen, e.g. by contact with H2 gas at an elevated temperature or with a H2 plasma subsequent to plasma ashing/etching. The invention enjoys particular utility in the formation of dual damascene openings in dielectric layers as part of metallization processing of semiconductor IC devices.

Abstract: Deleterious poisoning of patterned photoresist masking layers accompanying plasma ashing/etching of photoresist and/or low-k dielectric layers is eliminated, or at least substantially reduced, by pretreating exposed surfaces of the low-k dielectric layer(s) with hydrogen, e.g., by contact with a hydrogen plasma prior to plasma ashing/etching. The invention enjoys particular utility in the formation of dual damascene openings in dielectric layers as part of metallization processing of semiconductor IC devices.