Abstract: A process for the formation of a capping layer on a conducting interconnect for a semiconductor device is provided, the process comprising the steps of: (a) providing one or more conductors in a dielectric layer, and (b) depositing a capping layer on an upper surface of at least some of the one or more conductors, characterised in that the process further includes: (c) the step of, prior to depositing the capping layer, reacting the dielectric layer with an organic compound in a liquid phase, the said organic compound having the following general formula: (I) where X is a functional group, R is an organic group or a organosiloxane group, Y1 is either a functional group or an organic group or organosiloxane group, and Y2 is either a functional group or an organic group or organosiloxane group, and where the functional group(s) is/are independently selected from the following: NH2, a secondary amine, a tertiary amine, acetamide, trifluoroacetamide, imidazole, urea, OH, an alkyoxy, acryloxy, acetate, SH, an alky

Abstract: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

Abstract: Utilizing magnetic features located on different structures having semiconductor devices to align the structures when contacting the structures together. The magnetic features on each structure are of opposite polarity and provide magnetic forces for alignment of the structures. The magnetic forces can also be used to sense position and move the structures into an aligned position. In some examples, the structures include die with semiconductor devices. In one example, the structures are wafers with multiple die. In other examples, one of the structures is a die and the other is a wafer.

Abstract: A method for making a semiconductor device includes cleaning a semiconductor wafer after a chemical mechanical polishing (CMP) process to remove or reduce particles of copper, a corrosion inhibitor such as triazole, and a copper oxide layer on the copper layer. In order to prepare for plating the copper layer with a layer that functions as a barrier to copper migration or diffusion, the surface of the copper layer and the dielectric layer are treated with an oxidant, a surfactant, and copper-chelating agent. The copper-chelating is preferably a mild acid such as an organic acid. The oxidant is particularly useful in removing the corrosion inhibitor. The barrier layer, preferably conductive, is then plated on the surface of the copper layer. Subsequent interlayer dielectric layers and copper layers follow that can use the same process.

Abstract: A diffusion barrier stack is formed by forming a layer comprising a metal over a conductor that includes copper; and forming a first dielectric layer over the layer, wherein the dielectric layer is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer prevents oxidation of the layer. In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer and the second layer is a dielectric layer. The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor.

Abstract: One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.