Abstract: The present invention relates to a method for manufacturing TFTs in which a gate electrode is first formed on a transparent glass substrate by depositing and patterning a first metal layer. Next, a first insulating layer, a semiconductor layer, impurity-containing semiconductor layer and a second insulating layer are deposited over the first metal layer and the substrate surface. The insulating layer is patterned followed by deposition of a second metal layer. First portions of the second metal layer and the impurity-containing semiconductor layer along with part of the second insulating layer are etched over the gate electrode (thereby forming source and drain electrodes) at the same time second portions of the second metal layer and impurity-containing semiconductor layer and portions of the semiconductor layer laterally spaced from the gate electrode are etched. As a result, the number of etching steps is reduced, and the second insulating layer controls the etching speed.

Abstract: A liquid crystal display is disclosed including a redundancy line formed between a substrate and a gate line or data line, in which the redundancy line is formed along but offset and zigzag from the data line. The data line is prevented from being opened due to the stress generated between the data line and redundancy line.

Abstract: A semiconductor device requiring fewer masking steps to manufacture. The semiconductor device includes the following layers (from bottom up): (1) a substrate; (2) a gate electrode formed on a first portion of the substrate; (3) a first semiconductor layer overlying the gate electrode and a second portion of the substrate adjacent the first portion; (4) first and second spaced doped semiconductor layers provided on a surface of the first semiconductor layer and defining an exposed portion of the first semiconductor layer; (5) first and second insulating layer respectively provided on the first and second spaced doped semiconductor layers adjacent a periphery of the exposed portion of the first semiconductor layer; (6) a first electrode overlying and in contact with the doped semiconductor layer and the first insulating layer; and (7) a second electrode overlying and in contact with the second doped semiconductor layer and the second insulating layer.