Abstract: An associative main store, having application in computing technology and automation, avoids disadvantages of well-known associative main stores which have a great number of external outputs due to the presence of inputs to address every memory cell, and which require that the addresses be stored in an extra external device. The invention is able to increase the digits of the associative conditions facilitating operation by the user and providing extended functional possibilities.

Abstract: An arithmetic device having successive arithmetic registers connected in cascade, with buffer registers at each end of the cascade. An information exchange circuit bidirectionally connected to all the arithmetic registers for controlling information transfer therebetween such that the first register is connected to all of the other registers and every other register is also connected to a preceding and a succeeding register.

Abstract: A register circuit for processing information in accordance with a given instruction set or set of transformation comprises N registers each having an input and an output and provided in a sequence R.sub.1, R.sub.2, R.sub.3, . . . R.sub.N, each register having n digits where N and n are integers. The output of the first register R.sub.1 is connected to a first bus while its input is connected to a second bus. All of the other registers R.sub.2, R.sub.3, . . . R.sub.N have their inputs connected to the first bus and their outputs to the second bus by respective strobe circuits. The strobe circuits of each of the buses R.sub.3 . . . R.sub.N are connected to respective control inputs a.sub.3 . . . a.sub.N. Additional control inputs a.sub.1 and a.sub.2 are connected to an OR-gate whose output is applied to the input strobe circuit of register R.sub.2 while the input a.sub.2 is also applied directly to the output strobe circuit of register R.sub. 2.

Abstract: A stack memory device which comprises a memory stack of n-bit registers with gating circuiting controlled by code inverters to allow first in - first out, first in - last out, last in - first out and other selective transfers of data within the stack.