Abstract: An interposer includes an upper surface for coupling to a chip, a lower surface for coupling to a package substrate, and redistribution layers between the upper surface and the lower surface and including routed conductive lines. A respective one of the routed conductive lines extend between a first location and a second location and includes two or more traces extending substantially in parallel between the first location and the second location. Related devices and methods are also described.

Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.

Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.

Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.

Abstract: Apparatuses, systems, and methods for high-pass filtering pre-emphasis circuits. A device may use a pre-emphasis driver to provide a multi-level signal based on multiple binary signals. The pre-emphasis driver includes a primary driver coupled in parallel with at least one equalizer path, each of which includes an equalizer driver and a filtering element. The filtering element may be an AC filtering element, such as a capacitor. The equalizer paths may contribute equalized signal(s) which have a high-pass filtering behavior. The pre-emphasis circuit may combine the primary signal from the primary driver and the equalized signals to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver may be a pulse amplitude modulated (PAM) driver, such as a PAM4 driver with four levels of the multi-level driver.

Abstract: Methods, systems, and devices for crosstalk cancellation for signal lines are described. In some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. The device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. The device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.

Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.

Abstract: Apparatuses, systems, and methods for high-pass filtering pre-emphasis circuits. A device may use a pre-emphasis driver to provide a multi-level signal based on multiple binary signals. The pre-emphasis driver includes a primary driver coupled in parallel with at least one equalizer path, each of which includes an equalizer driver and a filtering element. The filtering element may be an AC filtering element, such as a capacitor. The equalizer paths may contribute equalized signal(s) which have a high-pass filtering behavior. The pre-emphasis circuit may combine the primary signal from the primary driver and the equalized signals to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver may be a pulse amplitude modulated (PAM) driver, such as a PAM4 driver with four levels of the multi-level driver.

Abstract: Apparatuses, systems, and methods for high-pass filtering pre-emphasis circuits. A device may use a pre-emphasis driver to provide a multi-level signal based on multiple binary signals. The pre-emphasis driver includes a primary driver coupled in parallel with at least one equalizer path, each of which includes an equalizer driver and a filtering element. The filtering element may be an AC filtering element, such as a capacitor. The equalizer paths may contribute equalized signal(s) which have a high-pass filtering behavior. The pre-emphasis circuit may combine the primary signal from the primary driver and the equalized signals to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver may be a pulse amplitude modulated (PAM) driver, such as a PAM4 driver with four levels of the multi-level driver.

Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. The memory device may use pulse amplitude modulation (PAM) signaling (e.g., PAM4) that is synchronized with a clock signal using a double data rate (DDR) to communicate information with a host device. The memory device may include a first circuit for determining voltage levels of sampling events associated with a rising edge of the clock signal and a second circuit for determining voltage levels of sampling events associated with a falling edge of the clock signal. A feedback circuit may receive a feedback signal associated with the first circuit and modify the signal input into the second circuit. The feedback circuit may include a latch circuit configured to receive portions of the signal and receive a first control signal and a second control signal to tune portions of the signal.

Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. The memory device may use pulse amplitude modulation (PAM) signaling (e.g., PAM4) that is synchronized with a clock signal using a double data rate (DDR) to communicate information with a host device. The memory device may include a first circuit for determining voltage levels of sampling events associated with a rising edge of the clock signal and a second circuit for determining voltage levels of sampling events associated with a falling edge of the clock signal. A feedback circuit may receive a feedback signal associated with the first circuit and modify the signal input into the second circuit. The feedback circuit may include a latch circuit configured to receive portions of the signal and receive a first control signal and a second control signal to tune portions of the signal.

Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. The memory device may use pulse amplitude modulation (PAM) signaling (e.g., PAM4) that is synchronized with a clock signal using a double data rate (DDR) to communicate information with a host device. The memory device may include a first circuit for determining voltage levels of sampling events associated with a rising edge of the clock signal and a second circuit for determining voltage levels of sampling events associated with a falling edge of the clock signal. A feedback circuit may receive a feedback signal associated with the first circuit and modify the signal input into the second circuit. The feedback circuit may include a latch circuit configured to receive portions of the signal and receive a first control signal and a second control signal to tune portions of the signal.

Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. The memory device may use pulse amplitude modulation (PAM) signaling (e.g., PAM4) that is synchronized with a clock signal using a double data rate (DDR) to communicate information with a host device. The memory device may include a first circuit for determining voltage levels of sampling events associated with a rising edge of the clock signal and a second circuit for determining voltage levels of sampling events associated with a falling edge of the clock signal. A feedback circuit may receive a feedback signal associated with the first circuit and modify the signal input into the second circuit. The feedback circuit may include a latch circuit configured to receive portions of the signal and receive a first control signal and a second control signal to tune portions of the signal.