Patents by Inventor M. Ceredig Roberts

M. Ceredig Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of Forming Trench Isolation in the Fabrication of Integrated Circuitry and Methods of Fabricating Integrated Circuitry
    Publication number: 20110300689
    Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.
    Type: Application
    Filed: August 16, 2011
    Publication date: December 8, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Robert D. Patraw, M. Ceredig Roberts, Keith R. Cook
  • Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
    Patent number: 8012847
    Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: September 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Patraw, M. Ceredig Roberts, Keith R. Cook
  • Methods of forming semiconductor constructions
    Patent number: 7557048
    Abstract: The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: July 7, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Chandra V. Mouli, M. Ceredig Roberts, Fernando Gonzalez
  • Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry
    Patent number: 7387940
    Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Robert D. Patraw, M. Ceredig Roberts, Keith R. Cook
  • Methods of forming semiconductor constructions
    Patent number: 7189662
    Abstract: The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: March 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Chandra V. Mouli, M. Ceredig Roberts, Fernando Gonzalez
  • Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry
    Publication number: 20060046426
    Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.
    Type: Application
    Filed: August 9, 2005
    Publication date: March 2, 2006
    Inventors: Gurtej Sandhu, Robert Patraw, M. Ceredig Roberts, Keith Cook