Patents by Inventor M. Clair Webb
M. Clair Webb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240362391Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Inventors: Ranjith KUMAR, Quan SHI, Mark T. BOHR, Andrew W. YEOH, Sourav CHAKRAVARTY, Barbara A. CHAPPELL, M. Clair WEBB
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Patent number: 12067338Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.Type: GrantFiled: January 26, 2022Date of Patent: August 20, 2024Assignee: Intel CorporationInventors: Ranjith Kumar, Quan Shi, Mark T. Bohr, Andrew W. Yeoh, Sourav Chakravarty, Barbara A. Chappell, M. Clair Webb
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Publication number: 20220149075Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Inventors: Ranjith KUMAR, Quan SHI, Mark T. BOHR, Andrew W. YEOH, Sourav CHAKRAVARTY, Barbara A. CHAPPELL, M. Clair WEBB
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Patent number: 11271010Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.Type: GrantFiled: September 20, 2017Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Ranjith Kumar, Quan Shi, Mark T. Bohr, Andrew W. Yeoh, Sourav Chakravarty, Barbara A. Chappell, M. Clair Webb
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Publication number: 20200357823Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.Type: ApplicationFiled: September 20, 2017Publication date: November 12, 2020Inventors: Ranjith KUMAR, Quan SHI, Mark T. BOHR, Andrew W. YEOH, Sourav CHAKRAVARTY, Barbara A. CHAPPELL, M. Clair WEBB
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Patent number: 10700039Abstract: A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.Type: GrantFiled: June 16, 2014Date of Patent: June 30, 2020Assignee: Intel CorporationInventors: Donald W. Nelson, M. Clair Webb, Patrick Morrow, Kimin Jun
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Patent number: 10297592Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.Type: GrantFiled: June 16, 2017Date of Patent: May 21, 2019Assignee: Intel CorporationInventors: Patrick Morrow, Kimin Jun, M. Clair Webb, Donald W. Nelson
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Patent number: 10068874Abstract: A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.Type: GrantFiled: June 16, 2014Date of Patent: September 4, 2018Assignee: Intel CorporationInventors: Donald W. Nelson, M Clair Webb, Patrick Morrow, Kimin Jun
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Publication number: 20170287905Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.Type: ApplicationFiled: June 16, 2017Publication date: October 5, 2017Inventors: Patrick Morrow, Kimin Jun, M. Clair Webb, Donald W. Nelson
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Patent number: 9721898Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.Type: GrantFiled: October 4, 2016Date of Patent: August 1, 2017Assignee: Intel CorporationInventors: Patrick Morrow, Don Nelson, M. Clair Webb, Kimin Jun, Il-Seok Son
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Patent number: 9685436Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.Type: GrantFiled: June 25, 2013Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Patrick Morrow, Kimin Jun, M. Clair Webb, Donald W. Nelson
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Publication number: 20170077389Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein.Type: ApplicationFiled: June 16, 2014Publication date: March 16, 2017Inventors: Donald W. NELSON, M Clair WEBB, Patrick MORROW, Kimin JUN
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Publication number: 20170069598Abstract: A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.Type: ApplicationFiled: June 16, 2014Publication date: March 9, 2017Inventors: Donald W. NELSON, M Clair WEBB, Patrick MORROW, Kimin JUN
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Publication number: 20170069597Abstract: A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.Type: ApplicationFiled: June 16, 2014Publication date: March 9, 2017Applicant: Intel CorporationInventors: Donald W. NELSON, M. Clair WEBB, Patrick MORROW, Kimin JUN
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Publication number: 20170025355Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.Type: ApplicationFiled: October 4, 2016Publication date: January 26, 2017Inventors: Patrick Morrow, Don Nelson, M. Clair Webb, Kimin Jun, II-Seok Son
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Patent number: 9490201Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.Type: GrantFiled: March 13, 2013Date of Patent: November 8, 2016Assignee: Intel CorporationInventors: Patrick Morrow, Don Nelson, M. Clair Webb, Kimin Jun, Il-Seok Son
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Publication number: 20160197069Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.Type: ApplicationFiled: June 25, 2013Publication date: July 7, 2016Inventors: Patrick Morrow, Kimin Jun, M. Clair Webb, Donald W. Nelson
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Patent number: 8860199Abstract: Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.Type: GrantFiled: February 4, 2009Date of Patent: October 14, 2014Assignee: Intel CorporationInventors: Bryan P. Black, Nicholas G. Samra, M. Clair Webb
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Patent number: 8519462Abstract: A 6F2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.Type: GrantFiled: June 27, 2011Date of Patent: August 27, 2013Assignee: Intel CorporationInventors: Yih Wang, M. Clair Webb, Nick Lindert, Swaminathan Sivakumar, Kevin X. Zhang, Dinesh Somasekhar
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Publication number: 20120326218Abstract: A 6F2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.Type: ApplicationFiled: June 27, 2011Publication date: December 27, 2012Inventors: Yih Wang, M. Clair Webb, Nick Lindert, Swaminathan Sivakumar, Kevin X. Zhang, Dinesh Somasekhar