Patents by Inventor M. Clair Webb

M. Clair Webb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240362391
    Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Ranjith KUMAR, Quan SHI, Mark T. BOHR, Andrew W. YEOH, Sourav CHAKRAVARTY, Barbara A. CHAPPELL, M. Clair WEBB
  • Patent number: 12067338
    Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Ranjith Kumar, Quan Shi, Mark T. Bohr, Andrew W. Yeoh, Sourav Chakravarty, Barbara A. Chappell, M. Clair Webb
  • Publication number: 20220149075
    Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.
    Type: Application
    Filed: January 26, 2022
    Publication date: May 12, 2022
    Inventors: Ranjith KUMAR, Quan SHI, Mark T. BOHR, Andrew W. YEOH, Sourav CHAKRAVARTY, Barbara A. CHAPPELL, M. Clair WEBB
  • Patent number: 11271010
    Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Ranjith Kumar, Quan Shi, Mark T. Bohr, Andrew W. Yeoh, Sourav Chakravarty, Barbara A. Chappell, M. Clair Webb
  • Publication number: 20200357823
    Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.
    Type: Application
    Filed: September 20, 2017
    Publication date: November 12, 2020
    Inventors: Ranjith KUMAR, Quan SHI, Mark T. BOHR, Andrew W. YEOH, Sourav CHAKRAVARTY, Barbara A. CHAPPELL, M. Clair WEBB
  • Patent number: 10700039
    Abstract: A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, M. Clair Webb, Patrick Morrow, Kimin Jun
  • Patent number: 10297592
    Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Kimin Jun, M. Clair Webb, Donald W. Nelson
  • Patent number: 10068874
    Abstract: A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, M Clair Webb, Patrick Morrow, Kimin Jun
  • Publication number: 20170287905
    Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: Patrick Morrow, Kimin Jun, M. Clair Webb, Donald W. Nelson
  • Patent number: 9721898
    Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Don Nelson, M. Clair Webb, Kimin Jun, Il-Seok Son
  • Patent number: 9685436
    Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Kimin Jun, M. Clair Webb, Donald W. Nelson
  • Publication number: 20170077389
    Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein.
    Type: Application
    Filed: June 16, 2014
    Publication date: March 16, 2017
    Inventors: Donald W. NELSON, M Clair WEBB, Patrick MORROW, Kimin JUN
  • Publication number: 20170069598
    Abstract: A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.
    Type: Application
    Filed: June 16, 2014
    Publication date: March 9, 2017
    Inventors: Donald W. NELSON, M Clair WEBB, Patrick MORROW, Kimin JUN
  • Publication number: 20170069597
    Abstract: A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.
    Type: Application
    Filed: June 16, 2014
    Publication date: March 9, 2017
    Applicant: Intel Corporation
    Inventors: Donald W. NELSON, M. Clair WEBB, Patrick MORROW, Kimin JUN
  • Publication number: 20170025355
    Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
    Type: Application
    Filed: October 4, 2016
    Publication date: January 26, 2017
    Inventors: Patrick Morrow, Don Nelson, M. Clair Webb, Kimin Jun, II-Seok Son
  • Patent number: 9490201
    Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Don Nelson, M. Clair Webb, Kimin Jun, Il-Seok Son
  • Publication number: 20160197069
    Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.
    Type: Application
    Filed: June 25, 2013
    Publication date: July 7, 2016
    Inventors: Patrick Morrow, Kimin Jun, M. Clair Webb, Donald W. Nelson
  • Patent number: 8860199
    Abstract: Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Bryan P. Black, Nicholas G. Samra, M. Clair Webb
  • Patent number: 8519462
    Abstract: A 6F2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Yih Wang, M. Clair Webb, Nick Lindert, Swaminathan Sivakumar, Kevin X. Zhang, Dinesh Somasekhar
  • Publication number: 20120326218
    Abstract: A 6F2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 27, 2012
    Inventors: Yih Wang, M. Clair Webb, Nick Lindert, Swaminathan Sivakumar, Kevin X. Zhang, Dinesh Somasekhar