Abstract: In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.

Abstract: In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.

Abstract: In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.

Abstract: A signal conditioner that includes a transition-detection module and a current-injection module. The transition-detection module is configured to receive a pair of differential signals from a data line and generate one or more comparator output signals and a transition-indication signal to indicate whether a transition has been detected on the differential signals. The current-injection module is configured to receive the comparator output signals and transition-indication signal from the transition-detection module, and generate appropriate currents for injection into the data line to boost edge rates of the differential signals when the transition-detection module detects a transition of the differential signals or remain high impedance when no transition occurs on the differential signals.

Abstract: In versions 1.1a and 1.2 of the DISPLAYPORT™ standard, capacitors are used between a sourcing circuit and a switch for the auxiliary channel. As a result, these capacitors are generally uncharged when the switch activates the auxiliary channel, which can result in errors. Here, a switch is employed that uses precharge circuits to precharge these capacitors. Thus, errors due to charging of these capacitors can be reduced.

Abstract: In versions 1.1a and 1.2 of the DISPLAYPORT™ standard, capacitors are used between a sourcing circuit and a switch for the auxiliary channel. As a result, these capacitors are generally uncharged when the switch activates the auxiliary channel, which can result in errors. Here, a switch is employed that uses precharge circuits to precharge these capacitors. Thus, errors due to charging of these capacitors can be reduced.

Abstract: In a method and apparatus for controlling damping and bandwidth in a phase locked loop (PLL), a loop filter is configured to have a dual path for charge pump current. A 3 dB bandwidth of the PLL is controlled by adjusting gain of a proportional current path. An integral current path includes a gating circuit to digitally control an amount of time an integral charge pump current received is passed through as an effective integral charge pump current. A resistor and capacitor (RC) circuit filters the proportional and effective integral charge pump currents, thereby providing a filtered input to a voltage controlled oscillator. Damping and hence peaking of the PLL is precisely controlled by sampling one of every p samples of the integral charge pump current to provide the effective integral charge pump current, p being an integer.

Abstract: In a method and apparatus for controlling damping and bandwidth in a phase locked loop (PLL), a loop filter is configured to have a dual path for charge pump current. A 3 dB bandwidth of the PLL is controlled by adjusting gain of a proportional current path. An integral current path includes a gating circuit to digitally control an amount of time an integral charge pump current received is passed through as an effective integral charge pump current. A resistor and capacitor (RC) circuit filters the proportional and effective integral charge pump currents, thereby providing a filtered input to a voltage controlled oscillator. Damping and hence peaking of the PLL is precisely controlled by sampling one of every p samples of the integral charge pump current to provide the effective integral charge pump current, p being an integer.