Patents by Inventor M. David McFarland

M. David McFarland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160350448
    Abstract: For state chart enhancement, a method encodes a logic design as a linear array that includes a plurality of logic states. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method calculates a combination map for a state transition between a start state and an end state of the plurality of logic states. In addition, the method identifies undefined binary input variable transitions for the state transition on the combination map. The method resolves the undefined binary input variable transitions.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 1, 2016
    Inventor: M. David McFarland
  • Publication number: 20160350450
    Abstract: For combination map based design, a method defines one or more logic elements including one or more binary output variables and one or more binary input variables. The method further assigns the one or more logic elements to a combination map. In addition, the method defines one or more logic element relationships between the logic elements on the combination map. The method encodes a plurality of fields of the combination map as a linear array that includes a plurality of logic states. Each logic state includes the one or more binary output variables, the one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 1, 2016
    Inventor: M. David McFarland
  • Publication number: 20160350446
    Abstract: For linear array hierarch navigation, a method encodes a logic design as a linear array with a plurality of logic states. The method displays combination maps of a plurality of fields at two or more successive display levels having a top display level and at least one lower display level. In addition, the method receives a selection of a first field of the plurality of fields. The method displays the first field and one or more successive combination maps for the first field. Each of the one or more successive combination maps is displayed with a field identifier of a predecessor field. In addition, the method displays relationship arrows linking the first field and each successive field of the first field.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 1, 2016
    Inventor: M. David McFarland
  • Publication number: 20160350449
    Abstract: For exceptional logic element management, a method encodes a logic design as a linear array that includes a plurality of logic states. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method identifies an exceptional logic element, wherein the exceptional logic element comprises one or more of an exceptional logic state, an exceptional state transition, and an exceptional input combination. In addition, the code displays the plurality of logic states excluding the exceptional logic elements from display.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 1, 2016
    Inventor: M. David McFarland
  • Publication number: 20160350668
    Abstract: For risk evaluation, a method encodes event data as a linear array that includes a plurality of logic states. The method estimates a success probability for each logic state and identifies path groups of the plurality of logic states. The logic states of each path group must all be healthy for each logic state to contribute to system success. The method further identifies each path combination of path groups and path nodes that result in system success. In addition, the method calculates a system success probability as a sum of success probabilities for each path combination. The success rate for each path combination is calculated as a product of the path group success probabilities for the path combination.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 1, 2016
    Inventor: M. David McFarland
  • Publication number: 20160350087
    Abstract: For parsing source code into a linear array, a method parses source code into a plurality of logic design elements. The method further identifies conditional logic for each logic design element. In addition, the method identifies computation logic for each logic design element. The method encodes each logic design element as a logic state of a plurality of logic states in a linear array. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 1, 2016
    Inventor: M. David McFarland
  • Patent number: 9396298
    Abstract: For linear array display, a method encodes a logic design as a linear array that includes a plurality of logic states. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method displays the linear array as a combination map comprising a plurality of fields. Each field represents a corresponding logic state.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: July 19, 2016
    Assignee: Assurant Design Automation LLC
    Inventor: M. David McFarland
  • Patent number: 6898563
    Abstract: A computer software tool for aiding in the design of combinatorial logic and sequential state machines comprising, according to the preferred embodiment, an apparatus and methods for representing and displaying a mathematical transform between a binary output variable and a set of binary input variables. The apparatus includes a computer software program which performs a method having the steps of separating input variables of a transform into successive fields, providing field combination maps having cells representative of binary combinations of field variables, assigning field combination maps of successive fields to each preceding field cell, and assigning binary values to field cell chains formed thereby. The computer software program also enables the visual display, on the display of a computer monitor, of the combination maps and the relationship between combination maps of preceding and successive fields.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: May 24, 2005
    Inventor: M. David McFarland