Patents by Inventor M. Dwayne Ward

M. Dwayne Ward has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6201757
    Abstract: A memory timing architecture which very accurately tracks the read and write timing of a memory over a wide range of array sizes, with separate read and write timing circuits. The read reset circuitry uses a plurality of dummy cells to gauge the time necessary to complete the read operation, while the write reset uses a single dummy cell to gauge the time necessary to complete the write operation. These circuits provide for a more accurately-timed feedback signal, which allows for increased speed while at the same time reducing power consumption and heat buildup.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: March 13, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: M. Dwayne Ward, Vikas Agrawal, George B. Jamison
  • Patent number: 5602780
    Abstract: A FIFO memory (4) provides serial to parallel and parallel to serial data conversion. A read frame buffer (40) and a write frame buffer (30) are coupled with a RAM array (22). Serial input data is stored temporarily into the write frame (30) of fixed width, n bits wide. Then, the entire n bit wide frame of stored serial input data is written into RAM array (22) at once in parallel. Data read in parallel from RAM array (22) is stored temporarily into the read frame (40) and thereafter provided serially to the FIFO output (53). By converting serial input to parallel input, overall chip size is reduced by reducing the number of pointers required because it is not necessary to address the RAM (22) individually when serially writing data into it. The read frame (40) coupled to the write frame (30) and to the serial input data. This allows data written into the FIFO to be immediately available and allows the read frame (40) to receive backfilled data from the write frame (30).
    Type: Grant
    Filed: October 20, 1993
    Date of Patent: February 11, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Benjamin C. Diem, M. Dwayne Ward
  • Patent number: 5596540
    Abstract: A FIFO memory (4) provides serial to parallel and parallel to serial data conversion. A read frame buffer (40) and a write frame buffer (30) are coupled with a RAM array (22). Serial input data is stored temporarily into the write frame (30) of fixed width, n bits wide. Then, the entire n bit wide frame of stored serial input data is written into RAM array (22) at once in parallel. Data read in parallel from RAM array (22) is stored temporarily into the read frame (40) and thereafter provided serially to the FIFO output (53). By converting serial input to parallel input, overall chip size is reduced by reducing the number of pointers required because it is not necessary to address the RAM (22) individually when serially writing data into it. The read frame (40) coupled to the write frame (30) and to the serial input data. This allows data written into the FIFO to be immediately available and allows the read frame (40) to receive backfilled data from the write frame (30).
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: January 21, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Benjamin C. Diem, M. Dwayne Ward
  • Patent number: 5365485
    Abstract: A clocked first-in first-out (FIFO) memory includes interleaved dual-port static random access memories (SRAM's) 32 and 36. The FIFO has status flags 44 to indicate empty and full conditions and two programmable flags, almost full and almost empty, to indicate when a selected number of words is stored in memory. In accordance with the present invention, the FIFO has retransmit capability, allowing previously read data to be accessed again. The FIFO is put in retransmit mode by providing a retransmit mode (RTM) input signal. This event causes the current read address stored in the read address registers 52 and 54, the interleave status in toggle circuit 22, the data in the data output latches 18 and 20 and in the pipeline latch 42, and the status flags 44, to be saved in shadow registers 64, 66, 24, (30, 62, 70, 116 and 120.
    Type: Grant
    Filed: November 22, 1993
    Date of Patent: November 15, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: M. Dwayne Ward, Kenneth L. Williams, Kevin J. Craig
  • Patent number: 5097442
    Abstract: A first-in, first-out memory (10) can store a programmable number of data words at respective address locations within a memory (76). A read address generator (50, 58) generates a read pointer for pointing to a read address location in the memory (76). A depth address generator (42) points to a depth address location in the memory that is displaced from the read address location by a predetermined number of address locations. This depth address generator (42) is incremented to a next read depth address responsive to a read pulse (20) issued from a read/write controller (12). A write address generator (80) points to a write address location within memory (76). A comparator (52) compares the value stored in the write address generator (42) to the read depth address location stored in depth address generator (42) and is operable to generate a FULL memory status flag (24) responsive to their equality.
    Type: Grant
    Filed: January 21, 1988
    Date of Patent: March 17, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: M. Dwayne Ward, Kenneth L. Williams