Patents by Inventor M. P. Galbiati

M. P. Galbiati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for forming CMOS transistors and MOS transistors of the drain extension type, with a low gate region resistance, in the same semiconductor substrate
    Publication number: 20040229438
    Abstract: A process is disclosed for forming, on a common semiconductor substrate, CMOS transistors and vertical or lateral MOS transistors on at least first and second portions, respectively, of the substrate. A first dielectric layer is formed on the substrate. A first semiconductor material layer is then formed on the first dielectric layer, in the first portion. A stack structure comprising a second dielectric layer, second semiconductor layer, and low-resistance layer is then formed over the substrate. First ports are defined in the second semiconductor layer and the low-resistance layer to provide gate regions of the vertical or lateral MOS transistors. The second semiconductor layer and the low-resistance layer are then removed from the first portion of the substrate by using the second dielectric layer as a screen. Second ports in the second dielectric layer and the second semiconductor layer are then defined to provide gate regions for the CMOS transistors.
    Type: Application
    Filed: December 23, 2003
    Publication date: November 18, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alessandro Moscatelli, Claudia Raffaglio, Alessandra Merlini, M. P. Galbiati