Abstract: An assembly and method for delivery of an analyte sensor including a reusable applicator having a proximal portion and a distal portion are disclosed. The reusable applicator can include a housing, a sensor carrier configured to releasably receive the first analyte sensor, a sharp carrier configured to releasably receive a sharp module, and an actuator movable relative to the housing.

Abstract: A swirler assembly for a combustor includes at least one swirler including a plurality of swirl vanes arrayed about an axis of the swirler. The plurality of swirl vanes includes a first ring of first sub-vanes and a second ring of second sub-vanes, the first ring of first sub-vanes and the second ring of second sub-vanes being separated by a gap therebetween.

Abstract: Methods, systems, and products for power reduction by removal of redundancy in clock pathways of VLSI circuits includes: calculating, based on a circuit design data file, a timing budget for an LCB (local clock buffer) and an associated group of latches receiving a clock signal from the LCB, where the circuit design data file includes a structural representation of a circuit design and timing data, identifying, based on the timing budget, a delay element to remove, the delay element included within a delay element chain associated with the LCB, and removing the delay element from the circuit design.

Abstract: The present invention relates to Compounds of Formula (I) and pharmaceutically acceptable salts or prodrug thereof. The present invention also relates to compositions comprising at least one compound of Formula (I), and methods of using the compounds of Formula (I) for treatment or prophylaxis of lysosomal storage diseases, neurodegenerative disease, cystic disease, cancer, or a diseases or disorders associated with elevated levels of glucosylceramide (GlcCer), glucosylsphingosine (GlcSph) and/or other glucosylceramide-based glycosphingolipids (GSLs).

Abstract: Dynamic campaign optimization systems and methods may be used to continuously test many alternative campaign configurations while allowing all configurations, including configurations formerly identified as successful and unsuccessful, to be re-tested in order to identify successful configurations that may previously have been identified as unsuccessful.

Abstract: A routing tool for routing nets within an integrated circuit design that includes: a processor; and a memory in communication with the processor and storing programming for the routing tool and a number of sets of equivalent wire codes. When the processor, alone or working with other processors, executes the programming, the routing tool routes each net in the integrated circuit design to satisfy parameters specified by a wire code associated with each net. Upon failure to route a net based on a current wire code assignment, the routing tool attempts to route the net using another wire code from a set of equivalent wire codes that includes the current wire code.

Abstract: Embodiments of a system and a method for detecting moisture within a structure can use a cementitious panel including a moisture sensor. The moisture sensor can comprise a moisture-sensing, passive RFID tag. A reader can be used to periodically interrogate the RFID moisture-sensing tag to determine whether the RFID moisture-sensing tag has been subjected to moisture. Systems and methods for detecting moisture within a structure can use at least one such cementitious panel in a structural assembly, such as a roof assembly, for example, to help detect a leak in the roof assembly through periodic monitoring of the installed cementitious panel(s).

Abstract: The present disclosure describes systems and methods for performing timing analysis of circuit designs. According to an embodiment, a method includes assigning a timing margin to a non-scan latch of a circuit design and performing a timing analysis on the circuit design using the timing margin for the non-scan latch to produce timing results for the circuit design. The timing results include a slack value. The method also includes calculating a credit based on the slack value and updating the slack value based on the credit.

Abstract: In some implementations, a device may receive first energy consumption information relating to a set of hardware components of a computing system. The device may receive second energy consumption information relating to a set of virtual machines associated with the computing system. The device may receive third energy consumption information relating to a set of software elements associated with the computing system. The device may determine an energy consumption of the computing system based on the first energy consumption information, the second energy consumption information, and the third energy consumption information. The device may identify, based on the energy consumption of the computing system, an energy optimization associated with a usage context of the computing system. The device may transmit a set of instructions to alter one or more parameters of the computing system to implement the energy optimization for the computing system.

Abstract: Scan chain optimization utilizing constrained single linkage clustering is disclosed. In an embodiment, a physical design tool identifies a placement of a plurality of latches in a circuit layout; generates, based on the placement, a set of latch clusters by applying constrained single-linkage agglomerative clustering to the plurality of latches; optimizes the set of latch clusters by redistributing latches across clusters; and generates a set of scan chains corresponding to the optimized set of latch clusters.

Abstract: The present subject matter relates to a system and a method for producing Hydrogen Peroxide in situ for sterilization of objects. In the system and the method, Hydrogen Peroxide solution of 30-35% concentration is processed to reach a target concentration value in a range of 90-95% of the resulting concentrated Hydrogen Peroxide.

Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit configured to generate an equalized signal, a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit is configured to monitor a frequency of the clock signal and activate an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. In response to activation of the indication signal, the clock generator circuit is configured to set the frequency of the clock signal to a particular frequency.

Abstract: A process of treating a feed in an adsorption separation zone comprising at least two adsorbent beds and a trim bed is disclosed. The process comprises displacing feed from a first adsorbent bed to a trim bed by feeding a desorbent from a second adsorbent bed to the first adsorbent bed while displacing spent desorbent from the trim bed. After discontinuing the first adsorbent bed displacement, an adsorber trim fluid to the first adsorbent bed to recover the remaining treated feed in the head. After discontinuing adsorber trim fluid to the first adsorbent bed; a trim displacement fluid is passed to the trim bed to displace feed from the trim bed.

Abstract: A phase detector circuit for use with a multi-level signaling communication protocol on a serial communication link is disclosed. The phase detector circuit employs multiple phase and logic circuits to detect data state changes between adjacent ones of voltage levels corresponding to different data states in the communication protocol, and generates early/late signals using the detected data state changes. The phase detector circuit statistically filters data state transitions between non-adjacent voltage levels to improve phase locking and reduce recovered clock jitter.

Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.

Abstract: Techniques for a dynamic radar mode modulation feature are described herein. A computer system associated with a device may implement a first radar configuration for a radar sensor. The first radar configuration may correspond to a first mode and comprise a first frame per second rate and a first difference threshold. The computer system may receive first data from the radar sensor in the first radar configuration. The computer system may determine a presence of an object within a field of view of the radar sensor based on the first data and the first difference threshold. The computer system may instruct the device to turn on based on determining the presence of the user. The radar sensor may be instructed to implement a second radar configuration associated with a second mode.

Abstract: Online advertisers may demand compliance with certain standards for the content of emails and other digital content with which its advertisements may be associated. Emails may contain control objects directing users to a web page showing content related to oil change coupons. However, in some systems, methods, and processes, a small variable proportion of users may instead be directed to a different sequence of pages to conduct a compliance check on the contents of the email received by the user. The compliance check sequence of pages may offer the user an incentive to forward the email to a specified email address for subsequent compliance review. Delivery of an incentive may be conditioned on successful receipt of the forwarded email.

Abstract: Methods and systems for circuit design are described. A tool may detect a timing violation on a signal path connected to a local clock buffer in a circuit model. The local clock buffer may be configured to generate a first clock signal having a first pulse width. The tool may determine a first metric associated with a first type of timing violation, and may determine a second metric associated with a second type of timing violation different from the first type of timing violation. The detected timing violation may be one of the first type and second type of timing violations. The tool may, based on the first metric and the second metric, determine whether to retain the generation of the first clock signal or to configure the local clock buffer to generate a second clock signal having a second pulse width different from the first pulse width.

Abstract: A method, system, and computer program product are disclosed for implementing enhanced noise impact on function (NIOF) analysis of an IC design having nets in multiple different variable voltage domains next to each other and modeling all multiple worst-case victim-aggressor voltage configurations in a single run leveraging noise abstracts characterized at a single voltage corner. The NIOF analysis enables accurately identifying incorrect victim switching or functional fails, effectively and efficiently providing design verification and the ability to sign-off an IC design with a single run, and enable modifying an integrated circuit design to fix NIOF failures, and fabricating an integrated circuit.

Abstract: A computer-implemented method includes receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip. Further, the method includes extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design. Further, the method includes predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block, the predicting performed using a pre-trained machine learning model. Further, the method includes using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.