Abstract: The design of a universally testable logic element from which combinational and sequential logic circuits can be formed is disclosed. The logic element is designed to operate as a NAND gate, NOR gate, or other functionally complete logic function in its normal mode. In a first test mode, the element functions like an OR gate. In a second test mode, the element functions like an AND gate. By building a circuit with such a logic element, the circuit can be tested for all classical stuck-at-zero and stuck-at-one faults with a minimal number of test patterns. Methods of testing both combinational and sequential circuits formed from such logic elements are also disclosed.