Patents by Inventor M. Shahidul Haque

M. Shahidul Haque has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6844248
    Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: January 18, 2005
    Assignee: The Trustees of the University of Arkansas
    Inventors: Hameed A. Naseem, M. Shahidul Haque, William D. Brown
  • Publication number: 20040106227
    Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.
    Type: Application
    Filed: July 14, 2003
    Publication date: June 3, 2004
    Applicant: The Board of Trustees of the University of Arkansas
    Inventors: Hameed A. Naseem, M. Shahidul Haque, William D. Brown
  • Patent number: 6613653
    Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: September 2, 2003
    Assignee: The Board of Trustees of the University of Arkansas
    Inventors: Hameed A. Naseem, M. Shahidul Haque, William D. Brown
  • Publication number: 20020055240
    Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.
    Type: Application
    Filed: December 31, 2001
    Publication date: May 9, 2002
    Applicant: The Board of Trustees of the Univ. of Arkansas
    Inventors: Hameed A. Naseem, M. Shahidul Haque, William D. Brown
  • Patent number: 6339013
    Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: January 15, 2002
    Assignee: The Board of Trustees of the University of Arkansas
    Inventors: Hameed A. Naseem, M. Shahidul Haque, William D. Brown