Abstract: A central processing unit (CPU) with facilities for debug support. The debug support facilities include debug support unit (DSU), a debug support interface bus, and a diagnostic instrument. During an execution trace, the DSU transmits trace data such as an instruction address and a trace status via the bus to the diagnostic instrument. Instruction addresses are sent in 4-bit segments in one clock cycle during a trace. Trace status includes an indication of non-sequential instruction execution by the Instruction Unit (IU). A control bit is used to toggle a hold on IU operation where a non-sequential instruction is encountered in trace mode. The diagnostic instrument uses trace data provided by the DSU to generate a complete execution trace in real-time. During breakpoint operations, input such as a debug instruction is provided by the diagnostic instrument via the debug support interface bus to the CPU for execution thereby.