Patents by Inventor M. Tsai
M. Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250094567Abstract: In an embodiment, a processor includes hardware circuitry which may be used to authenticate instruction operands. The processor may execute instructions that perform operand authentication both speculatively and non-speculatively. During speculative execution of such instructions, the processor may execute authentication such that no differences in observable state of the processor, relative to authentication result, are detectable via a side channel. During speculative execution, a result of authentication may be deferred until speculative execution of the instruction, and additional instructions, may be completed. Upon resolution of a condition that indicates acceptance of the speculative execution, a speculative execution result may cause a processor exception and stalling of execution at the instruction to be performed.Type: ApplicationFiled: November 15, 2023Publication date: March 20, 2025Applicant: Apple Inc.Inventors: John D Pape, Deepankar Duggal, Christopher M Tsay, Andrew H Lin, Corey C Stappenbeck
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Publication number: 20240311319Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.Type: ApplicationFiled: May 24, 2024Publication date: September 19, 2024Inventors: Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Mridul Agarwal, Christopher M. Tsay, Gideon N. Levinsky, Shih-Chieh Wen, Lior Zimet
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Patent number: 12007920Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.Type: GrantFiled: April 17, 2023Date of Patent: June 11, 2024Assignee: Apple Inc.Inventors: Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Mridul Agarwal, Christopher M. Tsay, Gideon N. Levinsky, Shih-Chieh Wen, Lior Zimet
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Patent number: 11806836Abstract: A composition is provided that comprises a calcium carbonate slurry. The calcium carbonate slurry comprises a plurality of calcium carbonate particles suspended in a solution, where the solution comprises a dispersant and an anionic surfactant. The concentration of the calcium carbonate particles in the calcium carbonate slurry is equal to or less than about 2.0 wt. %.Type: GrantFiled: December 6, 2021Date of Patent: November 7, 2023Assignee: Illumina, Inc.Inventors: Robert Yang, Samantha K. Brittelle, You-Jung Cheng, Scott William Bailey, James M. Tsay
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Publication number: 20230333851Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Inventors: Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky, Richard F. Russo, Christopher M. Tsay
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Publication number: 20230251985Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Mridul Agarwal, Christopher M. Tsay, Gideon N. Levinsky, Shih-Chieh Wen, Lior Zimet
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Patent number: 11720360Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.Type: GrantFiled: September 8, 2021Date of Patent: August 8, 2023Assignee: Apple Inc.Inventors: Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky, Richard F. Russo, Christopher M. Tsay
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Patent number: 11630789Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.Type: GrantFiled: April 30, 2021Date of Patent: April 18, 2023Assignee: Apple Inc.Inventors: Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Mridul Agarwal, Christopher M. Tsay, Gideon N. Levinsky, Shih-Chieh Wen, Lior Zimet
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Patent number: 11422821Abstract: A system and method for efficiently handling instruction execution ordering. In various embodiments, a processor includes multiple execution lanes, each executing instructions of a particular type, which are not executed by one or more of the other execution lanes. The instruction queue includes one queue for each particular execution lane. Control logic identifies a current youngest age used in allocated entries of the multiple queues, and determines a starting age based on the identified current youngest age and the number of instructions to be issued. Beginning with the determined starting age, ages (in program order) are assigned to a group of instructions being allocated in the multiple queues. Ages of entries in the multiple queues are updated for instructions not being issued based on the number of instructions being issued. Instructions being issued have age differences between them below a threshold.Type: GrantFiled: September 4, 2018Date of Patent: August 23, 2022Assignee: Apple Inc.Inventors: James N. Hardage, Jr., Christopher M. Tsay, Mahesh K. Reddy
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Patent number: 11307756Abstract: A method and system for providing absolute and zone coordinate mapping with graphic animations include presenting a user interface in an inactive state, wherein a background graphic animation and a user interface object graphic animation are presented on the user interface in an inactive format. The method and system also include determining that a touch input is provided on a touchpad to map a selected user interface object presented on the user interface based on an absolute mapped position of the touch input received on the touchpad. The method and system additionally include presenting the user interface in an active state, wherein the background graphic animation and the user interface object graphic animation are presented on the user interface in an active format.Type: GrantFiled: October 28, 2019Date of Patent: April 19, 2022Assignee: HONDA MOTOR CO., LTD.Inventors: Steven Feit, Ross Cameron Miller, Jessica Champi, Shaun Westbrook, Michael M. Tsay
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Publication number: 20220089910Abstract: A composition is provided that comprises a calcium carbonate slurry. The calcium carbonate slurry comprises a plurality of calcium carbonate particles suspended in a solution, where the solution comprises a dispersant and an anionic surfactant. The concentration of the calcium carbonate particles in the calcium carbonate slurry is equal to or less than about 2.0 wt. %.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Inventors: Robert Yang, Samantha K. Brittelle, You-Jung Cheng, Scott William Bailey, James M. Tsay
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Publication number: 20220083338Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.Type: ApplicationFiled: September 8, 2021Publication date: March 17, 2022Inventors: Jeff Gonion, John H. Kelm, James Vash, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky, Richard F. Russo, Christopher M. Tsay
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Publication number: 20220083484Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.Type: ApplicationFiled: April 30, 2021Publication date: March 17, 2022Inventors: Jeffrey E. Gonion, Charles E. Tucker, Tal Kuzi, Richard F. Russo, Mridul Agarwal, Christopher M. Tsay, Gideon N. Levinsky, Shih-Chieh Wen
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Patent number: 11264099Abstract: An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.Type: GrantFiled: November 5, 2020Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Dheeraj Srinivasan, Jeffrey M. Tsai, Ali Mohammadzadeh, Terry M. Grunzke
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Patent number: 11214712Abstract: A composition is provided that comprises a calcium carbonate slurry. The calcium carbonate slurry comprises a plurality of calcium carbonate particles suspended in a solution, where the solution comprises a dispersant and an anionic surfactant. The concentration of the calcium carbonate particles in the calcium carbonate slurry is equal to or less than about 2.0 wt. %.Type: GrantFiled: February 21, 2018Date of Patent: January 4, 2022Assignee: Illumina, Inc.Inventors: Robert Yang, Samantha K. Brittelle, You-Jung Cheng, Scott William Bailey, James M. Tsay
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Patent number: D948957Type: GrantFiled: May 17, 2019Date of Patent: April 19, 2022Assignee: Mosa Solutions, Inc.Inventors: Danny M. Tsai, Jeffrey M. Tsai, Michael Tsai
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Patent number: D948958Type: GrantFiled: May 17, 2019Date of Patent: April 19, 2022Assignee: Mosa Solutions, Inc.Inventors: Danny M. Tsai, Jeffrey M. Tsai, Michael Tsai
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Patent number: D948959Type: GrantFiled: May 17, 2019Date of Patent: April 19, 2022Assignee: Mosa Solutions, Inc.Inventors: Danny M. Tsai, Jeffrey M. Tsai, Michael Tsai
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Patent number: D948960Type: GrantFiled: May 17, 2019Date of Patent: April 19, 2022Assignee: Mosa Solutions, Inc.Inventors: Danny M. Tsai, Jeffrey M. Tsai, Michael Tsai
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Patent number: D960142Type: GrantFiled: May 6, 2019Date of Patent: August 9, 2022Assignee: Lenntek CorporationInventor: Danny M. Tsai