Patents by Inventor M V V Anil Krishna
M V V Anil Krishna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9645931Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.Type: GrantFiled: March 18, 2016Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Jason A. Cox, M V V Anil Krishna, Eric F. Robinson, Brian M. Rogers
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Publication number: 20160203079Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.Type: ApplicationFiled: March 18, 2016Publication date: July 14, 2016Inventors: JASON A. COX, M V V ANIL KRISHNA, ERIC F. ROBINSON, BRIAN M. ROGERS
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Patent number: 9323675Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.Type: GrantFiled: February 20, 2013Date of Patent: April 26, 2016Assignee: International Business Machines CorporationInventors: Jason A. Cox, M V V Anil Krishna, Eric F. Robinson, Brian M. Rogers
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Publication number: 20140237186Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.Type: ApplicationFiled: February 20, 2013Publication date: August 21, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason A. Cox, M V V Anil Krishna, Eric F. Robinson, Brian M. Rogers
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Patent number: 8386712Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.Type: GrantFiled: May 7, 2008Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Patent number: 7996618Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.Type: GrantFiled: January 28, 2011Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F Robinson, Sumedh W Sathaye, Jeffrey R Summers
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Publication number: 20110131394Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.Type: ApplicationFiled: January 28, 2011Publication date: June 2, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Patent number: 7934081Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.Type: GrantFiled: October 5, 2006Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Patent number: 7644233Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.Type: GrantFiled: October 4, 2006Date of Patent: January 5, 2010Assignee: International Business Machines CorporationInventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Patent number: 7610449Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.Type: GrantFiled: October 4, 2006Date of Patent: October 27, 2009Assignee: International Business Machines CorporationInventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Publication number: 20080250207Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.Type: ApplicationFiled: May 12, 2008Publication date: October 9, 2008Inventors: GORDON T. DAVIS, Richard W. Doing, John D. Jabusch, M.V.V. Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Publication number: 20080250206Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines is provided. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.Type: ApplicationFiled: May 7, 2008Publication date: October 9, 2008Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M.V.V. Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Publication number: 20080235500Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC).Type: ApplicationFiled: June 2, 2008Publication date: September 25, 2008Inventors: GORDON T. DAVIS, Richard W. Doing, John D. Jabusch, M. V.V. Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Publication number: 20080120468Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC).Type: ApplicationFiled: November 21, 2006Publication date: May 22, 2008Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Publication number: 20080114964Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.Type: ApplicationFiled: November 14, 2006Publication date: May 15, 2008Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Publication number: 20080098176Abstract: A method and apparatus implement memory accesses to a memory using an open page mode with data prefetching. A central processor unit issues memory commands. A memory controller receiving the memory commands, identifies a data prefetching command. The memory controller checks whether a next sequential line for the identified prefetch command is within the page currently being accessed, and responsive to identifying the next sequential line being within the current page, the current command is processed and the current page left open.Type: ApplicationFiled: October 18, 2006Publication date: April 24, 2008Inventors: M. V. V. Anil Krishna, Michael Raymond Trombley, Steven Paul VanderWeil
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Publication number: 20080086595Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.Type: ApplicationFiled: October 4, 2006Publication date: April 10, 2008Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M. V. V. Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Publication number: 20080086596Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.Type: ApplicationFiled: October 4, 2006Publication date: April 10, 2008Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M. V. V. Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Publication number: 20080086597Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.Type: ApplicationFiled: October 5, 2006Publication date: April 10, 2008Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M. V. V. Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Publication number: 20080077778Abstract: Register renaming as contemplated by this invention allows processor hardware to use a larger set of registers than the architected registers visible to the compiler. This larger set of registers is called the physical register file. Thus, dynamically renaming every compiler-suggested architected register to a microarchitecture-specific physical register, allows the processor to overcome name dependencies and the hazards (pipeline slowdowns) induced by name dependencies. The invention here described differs from prior renaming techniques in that it extracts significant benefit from renaming with a fraction of the number of physical registers previously used for this process. The invention therefore also simplifies the logic involved in supporting the use of the physical registers.Type: ApplicationFiled: September 25, 2006Publication date: March 27, 2008Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaya, Jeffrey R. Summers