Abstract: A functional-redundancy checking logic for checking identical chips whose outputs are time-variant programmable. Window logic (40, 60) on each chip creates a window associated with each programmed transition, set pulse (14) and reset pulse (15). For the set pulse (14), on the rising edge (42) of the window, an error flip-flop (50) is set. The flip-flop is merely set at this time; an error is not flagged. The window remains open for a fixed time period. During the time period that the window is open, if the output pin (24) is ever correctly asserted, then the flip-flop (50) is reset, thus clearing the error flag. However, if the pin (24) always remains incorrectly asserted, indicating an error, then the error flip-flop (50) remains set. When the window closes on the falling edge (46) of the window pulse, an error report pulse is created via the AND (52). The value on the flip-flop (50) at this time is reported as an error (54). An identical circuit checks the programmable reset pulse ( 15).

Abstract: In order for any failure of the power supply unit for two read-write memories which are operable in parallel, not to result in irreversible damage to data, two parallel power supply circuits are provided for the operation of the memories. Each power supply circuit is capable of supplying the operating current of one of the memories and the standby current of the remaining memory. Each of the power supply circuits in the power supply is buffered with capacitors in such a manner that, upon a fault in one of the power supply circuits, the output voltage, as soon as the capacitive buffer declines from a normal operating voltage to a threshold voltage and to a minimum operating voltage, data secure current reducing steps are taken.

Abstract: The waveform of a strobe type signal (70) is specified by two bit strings (72, 74) stored in the RAM (20), one bit string (72) denoting when the strobe is to be reset and the other (74) denoting when the strobe is to be set. The bit positions in the bit strings correspond with clock cycles (76) taken for a DRAM memory access. The bit positions are written by means of addressable registers (71) corresponding to rows (e.g. 80-87) of the RAM. A one bit in the set bit string (72) causes the signal (70) to be asserted in the corresponding clock cycle of the request. A one bit in the reset bit string causes the signal (70) to be de-asserted in the corresponding clock cycle of the request. The set and reset times are fine-tuned to a fraction of a cycle by providing a multi-bit fractional cycle index field (78) to accompany each bit string. If a two bit quarter cycle index (QCI) field is used, the boundaries of the quarter cycles are numbered from 0 to 3.