Patents by Inventor Ma Phoo Pwint Hlaing

Ma Phoo Pwint Hlaing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9620557
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xu Sheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9397058
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: July 19, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Publication number: 20160104731
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 14, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xu Sheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9252172
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9171769
    Abstract: A semiconductor device has a plurality of semiconductor die mounted active surface to a carrier. An encapsulant is deposited over semiconductor die and carrier. Openings are formed through a surface of the encapsulant to divide the encapsulant into discontinuous segments. The openings have straight or beveled sidewalls. The openings can be formed partially through the surface of the encapsulant in an area between the semiconductor die. The openings can be formed partially through the surface of the encapsulant over the semiconductor die. The openings can be formed through the encapsulant in an area between the semiconductor die. A portion of the surface of the encapsulant is removed down to a bottom of the openings. The carrier is removed. An interconnect structure is formed over the encapsulant and the semiconductor die. The encapsulant is cured prior to or after forming the openings.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: October 27, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9142522
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 22, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Publication number: 20150091165
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 2, 2015
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Patent number: 8963326
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Publication number: 20130140691
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Publication number: 20130134580
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Publication number: 20120306038
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Publication number: 20120139120
    Abstract: A semiconductor device has a plurality of semiconductor die mounted active surface to a carrier. An encapsulant is deposited over semiconductor die and carrier. Openings are formed through a surface of the encapsulant to divide the encapsulant into discontinuous segments. The openings have straight or beveled sidewalls. The openings can be formed partially through the surface of the encapsulant in an area between the semiconductor die. The openings can be formed partially through the surface of the encapsulant over the semiconductor die. The openings can be formed through the encapsulant in an area between the semiconductor die. A portion of the surface of the encapsulant is removed down to a bottom of the openings. The carrier is removed. An interconnect structure is formed over the encapsulant and the semiconductor die. The encapsulant is cured prior to or after forming the openings.
    Type: Application
    Filed: December 6, 2010
    Publication date: June 7, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing