Abstract: A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.

Abstract: A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a Galois multiply instruction. The execution unit includes a carryless multiplier configured to multiply operands of the Galois multiply instruction to generate a product. The execution unit further includes a modular reduction circuit configured to receive the product and determine, based on a logical combination of the product and a fixed polynomial, a reduced product having a fewer number of bits than the product. The execution unit is configured to store the reduced product to the architected register file as a result of the Galois multiply instruction.

Abstract: A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a key-generating instruction. The execution unit includes a key generation circuit that, responsive to a key-generating instruction, iteratively applies a cryptographic function to a sequence of iteration inputs beginning with an encryption key obtained from the architected register file and stores, within the architected register file, a decryption key obtained from at least one iteration of the cryptographic function.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: A system and method for avoiding write back collisions. The system receives a plurality of instructions at a pipeline queue. Next an issue queue determines a number of cycles for each instruction of the plurality of instructions. The issue queue further determines if a collision will occur between at least two of the instructions. Additionally, the system determines in response to a collision between at least two of the instructions, a number of cycles to delay at least one of the at least two instructions. The instructions are then executed. The system then places the results of the instruction for instructions that had a calculated delay in a result buffer for the determined number of cycles of delay. After the determined number of cycles of delay, the system sends the results to a results mux. Once received at the results mux the results are written back to the register file.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: A system and method for avoiding write back collisions. The system receives a plurality of instructions at a pipeline queue. Next an issue queue determines a number of cycles for each instruction of the plurality of instructions. The issue queue further determines if a collision will occur between at least two of the instructions. Additionally, the system determines in response to a collision between at least two of the instructions, a number of cycles to delay at least one of the at least two instructions. The instructions are then executed. The system then places the results of the instruction for instructions that had a calculated delay in a result buffer for the determined number of cycles of delay. After the determined number of cycles of delay, the system sends the results to a results mux. Once received at the results mux the results are written back to the register file.

Abstract: A method to determine an oldest instruction in an instruction queue of a processor with multiple instruction threads, wherein each of the multiple instruction threads have a unique thread identifier. The method includes tagging each instruction thread, of the multiple instruction threads, in the instruction queue with a unique tag number according to a round-robin scheme, wherein the unique tag number includes the unique thread identifier for each instruction thread and a round number in the round-robin scheme. The method further includes selecting, for each instruction thread, of the multiple instruction threads, the instruction thread with a lowest tag number from the multiple instruction threads in the instruction queue that are tagged with an oldest round number from the round-robin scheme.

Abstract: Aspects of the invention include receiving, by a processor, a plurality of instructions at an instruction pipeline. The processor can further determine an operand bit field size for each of the received plurality of instructions. The processor can further compare the operand bit field size of at least a subset of the received instructions to a predetermined threshold. The processor can further fuse at least two of the received instructions that have an operand bit field size that meets the predetermined threshold. The processor can further perform an execution stage within the instruction pipeline to execute the received instructions, including the fused instructions.

Abstract: A computer system, processor, and method for processing information is disclosed. The system, processor and/or method includes at least one computer processor; a register file associated with the at least one processor, the register file having a plurality of entries for storing data where a whole entry has two halves, the register file having multiple ports to write data to the register file and multiple ports to read data from the register file; and one or more execution units associated with the register file, the execution units configured to read data from the register file and to write data to the register file, wherein the processor is configured to write either scalar data or vector data to a single register file entry.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor, a register file associated with the at least one processor, the register file having a plurality of entries for storing data and sliced into a plurality of register banks, each register bank having a portion of the plurality of entries for storing data, one or more write ports to write data to the register file entries, and a plurality of read ports to read data from the register file entries; one or more read multiplexors associated with one or more read ports of each register bank and configured to receive data from the respective register banks; and one or more write multiplexors associated with one or more of the register banks.

Abstract: A computer processing system is provided. The computer processing system includes a processor configured to execute a record form instruction cracked into two internal instructions. A first one of the two internal instructions executes out-of-order to compute a target register and a second one of the two internal instructions executes in-order to compute a condition register (CR) to improve a processing speed of the record form instruction.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor, a register file associated with the at least one processor, the register file having a plurality of entries for storing data and sliced into a plurality of register banks, each register bank having a portion of the plurality of entries for storing data, one or more write ports to write data to the register file entries, and a plurality of read ports to read data from the register file entries; one or more read multiplexors associated with one or more read ports of each register bank and configured to receive data from the respective register banks; and one or more write multiplexors associated with one or more of the register banks.

Abstract: A computer system, processor, and method for processing information is disclosed. The system, processor and/or method includes at least one computer processor; a register file associated with the at least one processor, the register file having a plurality of entries for storing data where a whole entry has two halves, the register file having multiple ports to write data to the register file and multiple ports to read data from the register file; and one or more execution units associated with the register file, the execution units configured to read data from the register file and to write data to the register file, wherein the processor is configured to write either scalar data or vector data to a single register file entry.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: The present disclosure relates to a method to execute successive dependent instructions from an instruction stream in a processor. In an embodiment, the invention relates to a method to execute successive dependent instructions from an instruction stream in a processor. The method may include identifying a first instruction and a second instruction. A given operand of a second instruction is an output of the first instruction of the pair. The first instruction is older than the second instruction. The method may include loading the operands of the first instruction and the second instruction. The method may include executing the first instruction and the second instruction.

Abstract: A method to determine an oldest instruction in an instruction queue of a processor with multiple instruction threads, wherein each of the multiple instruction threads have a unique thread identifier. The method includes tagging each instruction thread, of the multiple instruction threads, in the instruction queue with a unique tag number according to a round-robin scheme, wherein the unique tag number includes the unique thread identifier for each instruction thread and a round number in the round-robin scheme. The method further includes selecting, for each instruction thread, of the multiple instruction threads, the instruction thread with a lowest tag number from the multiple instruction threads in the instruction queue that are tagged with an oldest round number from the round-robin scheme.

Abstract: An arithmetic logic unit is disclosed that includes a first logical circuit that generates a first partial sum result from three operands in a first stage of a single clock cycle of a processor; a second circuit that generates a second partial result in the same first stage of the clock cycle of the processor; and an adder that receives the first partial result from the first logical circuit and the second partial result from the second circuit and generates a secondary result during a second stage of the single clock cycle of the processor. The arithmetic logic unit may optionally further include a backend circuit that performs additional arithmetic and logic functions in the same single clock cycle of the processor.