Patents by Inventor Maarten J. Van Dort

Maarten J. Van Dort has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5828099
    Abstract: An (E)EPROM is provided in which information is written with hot electrons generated in the channel current at the source side of the channel instead of at the drain side, as is usual. To obtain the electric field distribution in the channel 6 necessary for this, the gate oxide 10 is provided with a thickened portion 13 adjacent the source zone 4 so that locally a strong lateral electric field is induced in the channel at higher gate voltages. An efficient charge transport of electrons to the floating gate 9 is obtained through this lateral electric field in the channel and the comparatively high electric field in the gate oxide. The thickened portion of the gate oxide may be obtained in a simple manner through thermal oxidation. To prevent the formation of strong fields at the drain side of the channel, the drain is preferably provided with an LDD structure 5a which adjoins the gate oxide. As a result, Fowler-Nordheim tunnelling through this thin gate oxide may also be used for erasing.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: October 27, 1998
    Assignee: U.S. Philips Corporation
    Inventors: Maarten J. Van Dort, Andrew J. Walker
  • Patent number: 5786252
    Abstract: A deep diffusion of the back-gate region provided in a self-aligned manner with respect to the gate electrode is necessary in a DMOS transistor for obtaining a sufficiently high punch-through voltage between source and drain. The combination of a comparatively heavy back-gate implantation and a light source implantation and a heavy source implantation with spacer on the gate electrode, and the use of interstitial diffusion and accelerated diffusion owing to crystal damage render it possible to carry out said diffusion of the back-gate region at a comparatively low temperature, for example below 950 .degree. C. This renders it possible to integrate a DMOST into, for example, standard VLSI CMOS where first .delta.V.sub.th and channel-profile implantations are carried out, and subsequently the poly gates are provided, which means that a diffusion step at a temperature above 1,000 .degree. C. of long duration is no longer allowed.
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: July 28, 1998
    Assignee: U.S. Philips Corporation
    Inventors: Adrianus W. Ludikhuize, Maarten J. Van Dort
  • Patent number: 5561315
    Abstract: A programmable semiconductor memory with filament or point diodes in the intersections of a matrix system can be manufactured with minimum dimensions and thus with a very high density owing to the absence of alignment tolerances. A possible problem is then posed by the strong leakage currents which may arise during programming owing to punch-through between adjoining diodes. Decreasing the leakage current through the use of a higher background concentration of the region in which these diodes are formed is not possible because this reduces the breakdown voltage of the pn junctions of the diodes too much. According to the invention, a more strongly doped surface zone is provided in the region between the diodes, which zone is situated at least at a distance from the diode points. In a specific embodiment, the zone extends less deeply into the region than do the diodes.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: October 1, 1996
    Assignee: U.S. Philips Corporation
    Inventor: Maarten J. Van Dort