Abstract: A circuit comprising a cascode device comprising a field effect transistor. The field effect transistor includes a common body region. The field effect transistor also includes a plurality of source regions. The source regions form inputs of the cascode device. Each source region of the plurality of source regions is separated from each other source region of the plurality of source regions by the common body region. The field effect transistor further includes a common gate. The field effect transistor also includes a common drain region. The common drain region forms an output of the cascode device. The circuit may further include a plurality of groups of one or more current sources each group coupled to a respective one of the inputs of the cascode device, and a current output coupled to the output of the cascode device. A method of operating a current source circuit.

Abstract: A testing method and apparatus is disclosed for testing an integrated circuit device (100) which has a dedicated ground bias pad (121) connected across a high voltage electrostatic discharge clamp circuit (123) to a well-driving ground pad (122) by applying a first voltage to the dedicated ground bias pad to bias a wafer substrate (101) while simultaneously applying a second voltage to the well-driving ground pad to bias the well region (103), where the first and second voltage create a stressing voltage across a buried insulator layer (102, 105) in the integrated circuit device so that a screening test can be conducted to screen for a defect (106) in the buried insulator layer by measuring a leakage current.

Abstract: A testing method and apparatus is disclosed for testing an integrated circuit device (100) which has a dedicated ground bias pad (121) connected across a high voltage electrostatic discharge clamp circuit (123) to a well-driving ground pad (122) by applying a first voltage to the dedicated ground bias pad to bias a wafer substrate (101) while simultaneously applying a second voltage to the well-driving ground pad to bias the well region (103), where the first and second voltage create a stressing voltage across a buried insulator layer (102, 105) in the integrated circuit device so that a screening test can be conducted to screen for a defect (106) in the buried insulator layer by measuring a leakage current.

Abstract: Various embodiments are directed to electrostatic discharge (ESD) protection apparatus comprising a bipolar junction transistor (BJT) having terminals, a field-effect transistor (FET) having terminals, and a common base region connected to a recombination region. The BJT and the FET are integrated with one another and include a common region that is shared by the BJT and the FET. The BJT and FET collectively bias the common base region and prevent triggering of the BJT by causing a potential of the common base region to follow a potential of one of the terminals of the BJT in response to an excessive but tolerable non-ESD voltage change at one or more of the terminals.

Abstract: Various embodiments are directed to electrostatic discharge (ESD) protection apparatus comprising a bipolar junction transistor (BJT) having terminals, a field-effect transistor (FET) having terminals, and a common base region connected to a recombination region. The BJT and the FET are integrated with one another and include a common region that is shared by the BJT and the FET. The BJT and FET collectively bias the common base region and prevent triggering of the BJT by causing a potential of the common base region to follow a potential of one of the terminals of the BJT in response to an excessive but tolerable non-ESD voltage change at one or more of the terminals.

Abstract: Described herein is an N type extended drain transistor formed from a semiconductor on insulator (SOI) wafer. The transistor has a buried P type region formed by the selective implantation of P type dopants in a semiconductor layer of the wafer at a location directly below a drift region of the transistor. The transistor also includes a source located in a P well region and a drain. The buried P type region is in electrical contact with the P well region. The N type drift region, the source, and the drain are also located in a portion of the semiconductor layer surrounded by dielectric isolation. A buried dielectric layer located below the portion of the semiconductor layer electrically isolates the portion of the semiconductor layer from a semiconductor substrate located below the buried dielectric layer.

Abstract: Described herein is an N type extended drain transistor formed from a semiconductor on insulator (SOI) wafer. The transistor has a buried P type region formed by the selective implantation of P type dopants in a semiconductor layer of the wafer at a location directly below a drift region of the transistor. The transistor also includes a source located in a P well region and a drain. The buried P type region is in electrical contact with the P well region. The N type drift region, the source, and the drain are also located in a portion of the semiconductor layer surrounded by dielectric isolation. A buried dielectric layer located below the portion of the semiconductor layer electrically isolates the portion of the semiconductor layer from a semiconductor substrate located below the buried dielectric layer.

Abstract: A thyristor is disclosed comprising: a first region of a first conductivity type; a second region of a second conductivity type and adjoining the first region; a third region of the first conductivity type and adjoining the second region; a fourth region of the second conductivity type and comprising a first segment and a second segment separate from the first segment, the first segment and second segment each adjoining the third region; a first contact adjoining the first region; a second contact adjoining the first segment; and a trigger contact adjoining the second segment and separate from the second contact.

Abstract: A thyristor is disclosed comprising: a first region of a first conductivity type; a second region of a second conductivity type and adjoining the first region; a third region of the first conductivity type and adjoining the second region; a fourth region of the second conductivity type and comprising a first segment and a second segment separate from the first segment, the first segment and second segment each adjoining the third region; a first contact adjoining the first region; a second contact adjoining the first segment; and a trigger contact adjoining the second segment and separate from the second contact. Methods of triggering such a thyristor are also disclosed, as are circuits utilising one or more such thyristors.

Abstract: One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.

Abstract: Various exemplary embodiments relate to an isolation device including a semiconductor layer and an insulation layer. The insulation layer insulates a central portion of the semiconductor layer. A high voltage terminal connects to the insulation layer, a first low voltage terminal connects to a first non-insulated portion of the semiconductor layer, and a second low voltage terminal connects to a second non-insulated portion of the semiconductor layer. The first and second low voltage terminals are electrically connected via the semiconductor layer. A voltage applied to the high voltage terminal influences the conductance of the semiconductor layer. The high voltage terminal is galvanically isolated from the first and second low voltage terminals.

Abstract: One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.

Abstract: Various exemplary embodiments relate to an isolation device including a semiconductor layer and an insulation layer. The insulation layer insulates a central portion of the semiconductor layer. A high voltage terminal connects to the insulation layer, a first low voltage terminal connects to a first non-insulated portion of the semiconductor layer, and a second low voltage terminal connects to a second non-insulated portion of the semiconductor layer. The first and second low voltage terminals are electrically connected via the semiconductor layer. A voltage applied to the high voltage terminal influences the conductance of the semiconductor layer. The high voltage terminal is galvanically isolated from the first and second low voltage terminals.

Abstract: A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described.

Abstract: A semiconductor device has active region (30) and edge termination region (32) which includes a plurality of floating field regions (46). Field plates (54) extend in the edge termination region (32) inwards from contact holes (56) towards the active region (30) over a plurality of floating field regions (46). Pillars (40) may be provided.

Abstract: A PMOS device comprises a semiconductor-on-insulator (SOI) substrate having a layer of insulating material over which is provided an active layer of n-type semiconductor material. P-type source and drain regions are provided by diffusion in the n-type active layer. A p-type plug is provided at the source region, which extends through the active semiconductor layer to the insulating layer. The plug is provided so as to enable the source voltage applied to the device to be lifted significantly above the substrate voltage without the occurrence of excessive leakage currents.

Abstract: A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described.

Abstract: A power supply (10), comprising a rectifier (2) having an input side (3) connectable to an AC main power supply and an output side (6) connectable to a load; and a controllable shunt switch circuit (12), wherein the shunt switch circuit (12) is arranged on the input side (3) of the rectifier (2) to selectively shunt the rectifier (2) via the output side thereof.