Abstract: This disclosed technology relates to a programmable NAND flash memory and a method for operating the NAND flash memory. The method comprises applying a first voltage to the first gate and a pass voltage to one or more word lines to allow charge to inject into the channel layer and form charge packets. Each charge packet can be arranged next to one of the second gates. The method further comprises applying a programming voltage to the word lines to move the charge packets from the channel layer into the memory cells associated with the second gates next to which they are arranged.

Abstract: A memory device including at least one channel and a fluid including particles is provided. In one aspect, the channel includes a least some of the fluid. The memory device may further include an actuator configured to induce a movement of the particles in the channel; and a writing element configured to arrange the particles in a sequence, thereby yielding a sequence of particles in the channel. The particles may include first particles and second particles. The particles may be in a first state or a second state in the channel. In certain aspects, the channel is configured to preserve the sequence of the particles. The memory device may further include a reading element for detecting the sequence of the particles in the channel.

Abstract: A liquid electrochemical memory device is provided. In one aspect, the device includes a memory region for storing at least two bits, the memory region having a first volume; and a liquid electrolyte region fluidically connected to the memory region, the liquid electrolyte region having a second volume larger than the first volume. The device further includes a working electrode exposed to the memory region, and a counter electrode exposed to the liquid electrolyte region. The device also includes an electrolyte filling the memory region and the liquid electrolyte region, in physical contact with the working electrode and the counter electrode, the electrolyte including at least two conductive species. The device further includes a control unit for biasing the working electrode and the counter electrode.

Abstract: A charge-coupled device (CCD) memory is provided. In one aspect, the CCD memory is 3D integrated. The CCD memory can include a gate stack with a plurality of gate layers and spacer layers alternatingly arranged one on the other, and a plurality of semiconductor-based channels extending in the stack. The channels may be formed from a semiconductor oxide material. The CCD memory can include dielectric layers, wherein each dielectric layer is arranged between one of the channels and at least one of the gate layers. Each channel of the CCD memory can form, in combination with the gate layers and at least one of the dielectric layers, a string of charge storage capacitors, and each string of charge storage capacitors can be operable as a CCD register. The CCD memory can also include a readout layer, which can include a plurality of readout stages configured to individually readout stored charge from each of the CCD registers.

Abstract: A storage device configured to store data on a tape is provided. In one aspect, the storage device includes the tape, which is configured to store data, and a data head, which is configured to read and/or write data from and/or to the tape. The storage device further includes an actuator configured to move the tape in a length direction in a step-wise manner. The actuator can include a plurality of pulling electrodes, wherein each pulling electrode can be activated to exert a pulling force on the tape, and a plurality of clamping electrodes, wherein each clamping electrode can be activated to clamp the tape.

Abstract: A storage device configured to store data on a tape is provided. In one aspect, the storage device includes the tape, which is configured to store data, and a data head, which is configured to read and/or write data from and/or to the tape. The storage device further includes an actuator configured to move the tape in a length direction in a step-wise manner. The actuator can include a plurality of pulling electrodes, wherein each pulling electrode can be activated to exert a pulling force on the tape, and a plurality of clamping electrodes, wherein each clamping electrode can be activated to clamp the tape.

Abstract: A liquid electrochemical memory device is provided. In one aspect, the device includes a memory region for storing at least two bits, the memory region having a first volume; and a liquid electrolyte region fluidically connected to the memory region, the liquid electrolyte region having a second volume larger than the first volume. The device further includes a working electrode exposed to the memory region, and a counter electrode exposed to the liquid electrolyte region. The device also includes an electrolyte filling the memory region and the liquid electrolyte region, in physical contact with the working electrode and the counter electrode, the electrolyte including at least two conductive species. The device further includes a control unit for biasing the working electrode and the counter electrode.

Abstract: A memory device including at least one channel and a fluid including particles is provided. In one aspect, the channel includes a least some of the fluid. The memory device may further include an actuator configured to induce a movement of the particles in the channel; and a writing element configured to arrange the particles in a sequence, thereby yielding a sequence of particles in the channel. The particles may include first particles and second particles. The particles may be in a first state or a second state in the channel. In certain aspects, the channel is configured to preserve the sequence of the particles. The memory device may further include a reading element for detecting the sequence of the particles in the channel.

Abstract: The disclosed technology presents a device and a method, respectively, for generating an augmented reality (AR) image (or AR video). The device configures to obtain a first image of a scene, obtain a second image of an object, obtain a depth range, and capture a third image of only the parts of the scene inside the depth range. Further, the device configures to generate occlusion information based on the third image, and overlay the first image and the second image based on the occlusion information to generate the AR image.

Abstract: An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (?LED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts.

Abstract: A device for time delay and integration imaging comprises: an array of pixels being arranged in rows and columns extending in a first and second direction, respectively. Pixels may accumulate generated charges in response to received electro-magnetic radiation along each column. The rows comprise at least one lateral charge shifting row to selectively shift accumulated charges in a column to an adjacent column and a controller configured to receive at least two angle correction input values. Each angle correction input value is based on a received intensity of electro-magnetic radiation on a measurement line, wherein the at least two angle correction input values are acquired by measurement lines extending in directions defining different angles in relation to the second direction, wherein the controller is configured to, based on the received at least two angle correction input values, control activation of the at least one lateral charge shifting row.

Abstract: A pixel architecture comprises: an absorption layer, which is configured to generate charges in response to incident light; a semiconductor charge-transport layer, which is configured to transport the generated charges through the charge-transport layer, wherein one or more doped regions are arranged in the charge-transport layer, wherein the charge-transport layer comprises a bias region and a charge-dispatch region being associated with the bias region; an electric connection connecting to and providing a selectable bias voltage to the bias region; and at least one transfer gate, wherein the doped regions and the bias region are differently biased for driving transport of the generated charges towards the charge-dispatch region, and for controlling, together with the at least one transfer gate, transfer of charges from the charge-dispatch region to a charge node.

Abstract: The disclosed technology presents a device and a method, respectively, for generating an augmented reality (AR) image (or AR video). The device configures to obtain a first image of a scene, obtain a second image of an object, obtain a depth range, and capture a third image of only the parts of the scene inside the depth range. Further, the device configures to generate occlusion information based on the third image, and overlay the first image and the second image based on the occlusion information to generate the AR image.

Abstract: An imaging sensor is disclosed, comprising: a set of at least two charge-coupled device, CCD, sub-arrays, wherein each sub-array comprises pixels arranged in columns and rows, and each pixel being arranged to accumulate an electric charge proportional to an intensity of light incident on the pixel; a time delay and integration, TDI, clocking circuitry for controlling and timing transfer of accumulated electric charges between rows of pixels in a column direction in order to integrate the accumulated electric charges in each column of pixels; wherein each CCD sub-array further comprises a readout row for converting the integrated electric charge of each column of pixels into voltage or current, wherein the readout row comprises transistors enabling readout of the signal by the readout block; and a readout block which is arranged to receive input from selected readout rows and convert the input into digital domain or convert the input to a combined representation of pixel values based on the set of CCD sub-arra

Abstract: A method for controlling time delay and integration, TDI, imaging includes acquiring image information using an array of pixels being arranged in rows and columns. Each pixel is configured to generate an electric charge proportional to intensity of electro-magnetic radiation incident on the pixel. The pixels are configured to transfer generated charges along columns of the array for accumulating the generated charges in the pixels along the columns from a first row towards a second row in the array of pixels. The method further includes non-destructively sensing, at an intermediate row between the first and the second row, a signal level of accumulated charges in at least one column; and destructively sensing, at the second row, a signal level of accumulated charges in the at least one column.

Abstract: An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (?LED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts.

Abstract: A device for time delay and integration imaging comprises: an array of pixels being arranged in rows and columns extending in a first and second direction, respectively. Pixels may accumulate generated charges in response to received electro-magnetic radiation along each column. The rows comprise at least one lateral charge shifting row to selectively shift accumulated charges in a column to an adjacent column and a controller configured to receive at least two angle correction input values. Each angle correction input value is based on a received intensity of electro-magnetic radiation on a measurement line, wherein the at least two angle correction input values are acquired by measurement lines extending in directions defining different angles in relation to the second direction, wherein the controller is configured to, based on the received at least two angle correction input values, control activation of the at least one lateral charge shifting row.

Abstract: A pixel architecture comprises: an absorption layer, which is configured to generate charges in response to incident light; a semiconductor charge-transport layer, which is configured to transport the generated charges through the charge-transport layer, wherein one or more doped regions are arranged in the charge-transport layer, wherein the charge-transport layer comprises a bias region and a charge-dispatch region being associated with the bias region; an electric connection connecting to and providing a selectable bias voltage to the bias region; and at least one transfer gate, wherein the doped regions and the bias region are differently biased for driving transport of the generated charges towards the charge-dispatch region, and for controlling, together with the at least one transfer gate, transfer of charges from the charge-dispatch region to a charge node.

Abstract: An imaging sensor is disclosed, comprising: a set of at least two charge-coupled device, CCD, sub-arrays, wherein each sub-array comprises pixels arranged in columns and rows, and each pixel being arranged to accumulate an electric charge proportional to an intensity of light incident on the pixel; a time delay and integration, TDI, clocking circuitry for controlling and timing transfer of accumulated electric charges between rows of pixels in a column direction in order to integrate the accumulated electric charges in each column of pixels; wherein each CCD sub-array further comprises a readout row for converting the integrated electric charge of each column of pixels into voltage or current, wherein the readout row comprises transistors enabling readout of the signal by the readout block; and a readout block which is arranged to receive input from selected readout rows and convert the input into digital domain or convert the input to a combined representation of pixel values based on the set of CCD sub-arra

Abstract: A device for imaging comprising an image sensor is disclosed. The image sensor includes rows and columns of pixels. The image sensor further includes a first control structure for controlling transfer of accumulated electric charges from photo-active regions to transmission regions in pixels. The image sensor further includes a second control structure for controlling transfer of accumulated charge in the transmission region of each row to the adjacent row below. The first and second control structures control the image sensor to alternately transfer accumulated charges in photo-active regions to the transmission regions and transfer charges to the adjacent row below. The control structure includes a plurality of row structures which are arranged to select whether the charge in the photo-active regions of respective rows are added to the transmission region. Each row of pixels is controlled by one of the row structures of the first control structure.