Abstract: A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.

Abstract: A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.

Abstract: The present invention relates to a method and a circuit arrangement for protecting a connection terminal (CANH, CANL) of a semiconductor device against electrostatic discharge (ESD), wherein first and second common nodes (N1, N2) protected against ESD of respective first and second polarities are provided. Connection terminals are coupled via first diode means (D5, D6) to the first common node and via second diode means (D7, D8) to the second common node. Thus, several terminals or pins can share the same ESD protection device by connecting them to the first and second common nodes. Due to the fact that a diode requires a smaller chip area than a protection diode, the total chip area can be reduced.