Abstract: In a liquid crystal display apparatus, a set of write-in voltages are generated corresponding to a horizontal line signal of an input video frame so that they appear at end points of the column lines of a LCD panel. The row lines of the LCD panel are successively selected and the write-in voltages are supplied from the end points of the column lines to the liquid crystal cells of the selected row line for a variable write-in period. In order to compensate for shades-of-gray differences between the top and bottom of the LCD panel, the write-in period is increasingly varied as a function of the geometric distance from the selected row line to the end points of the column lines. The write-in period may be increasingly variable from a nominal value, or from a less-than-nominal value to the nominal value, or a combination of both.

Abstract: A display panel 13 having a plurality of pixels 14 each divided into P (P=3) sub-pixels 15a, 15b and 15c, and a source driver 12 for driving each pixel 14 in accordance with three J (=8)-bit data values corresponding to the sub-pixels 15a, 15b, and 15c, and a signal processing circuit 12 for distributing K(=12)-bit (K>J) input image data as M (M=6) time-shared frame data values and supplying the frame data values to the source driver 12 are arranged. 2K?J (=16) gray levels insufficient due to the difference between the numbers of bits of K-bit input image data and J-bit driving signals of the source driver 12 is realized by combinations of time-shared frame data of (P×M=18) ways performed for the sub-pixels 15a, 15b, and 15c in accordance with the M time-shared frame data values.

Abstract: In a liquid crystal display device where each unit pixel p arranged on a liquid crystal panel 101A is constituted by a plurality of pixels p1, p2, and p3, the pixels p1, p2, and p3 are divided into sub-pixels p11 and p12, sub-pixels p21, and p22, and sub-pixels p31 and p32, respectively. The liquid crystal display device is provided with driver ICs 201 and 202 for driving the sub-pixels p11, p21, and p31, and the sub-pixels p12, p22, and p32 constituting the pixels so that different gradation-brightness value characteristics may be given. Due to this, multi-gradation display can be performed.

Abstract: In a liquid crystal display device where each unit pixel p arranged on a liquid crystal panel 101A is constituted by a plurality of pixels p1, p2, and p3, the pixels p1, p2, and p3 are divided into sub-pixels p11 and p12, sub-pixels p21, and p22, and sub-pixels p31 and p32, respectively. The liquid crystal display device is provided with driver ICs 201 and 202 for driving the sub-pixels p11, p21, and p31, and the sub-pixels p12, p22, and p32 constituting the pixels so that different gradation-brightness value characteristics may be given. Due to this, multi-gradation display can be performed.

Abstract: A liquid crystal display control circuit receives a data enable signal DE in synchronization with per-line based display data from a computer, and thereby controls a liquid crystal display. A gate drive signal outputted from a gate driver 23 is generated according to a vertical clock signal VCK in synchronization with a rise of the signal DE. In order to avoid a variation in the period of charging the pixel electrodes which is caused by a delay in the rise timing of the signal DE and a delay in the signal VCK after the last line, a gate enable signal generation circuit 10 is provided in the liquid crystal display control circuit 1, whereby the extended output of the pulse of the gate drive signal caused by the above-mentioned delays is inhibited. This avoids display inhomogeneity caused by a variation in the data enable signal and the like.

Abstract: In a liquid crystal display apparatus, a set of write-in voltages are generated corresponding to a horizontal line signal of an input video frame so that they appear at end points of the column lines of a LCD panel. The row lines of the LCD panel are successively selected and the write-in voltages are supplied from the end points of the column lines to the liquid crystal cells of the selected row line for a variable write-in period. In order to compensate for shades-of-gray differences between the top and bottom of the LCD panel, the write-in period is increasingly varied as a function of the geometric distance from the selected row line to the end points of the column lines. The write-in period may be increasingly variable from a nominal value, or from a less-than-nominal value to the nominal value, or a combination of both.

Abstract: A display apparatus is composed of a pseudo gray level data processor generating pseudo gray level data having m bits based on input gray level data having n bits. The pseudo gray level data processor includes a state variable generator generating a state variable data having n−m bits, based on lower n−m bits of the input gray level data, an adder calculating a sum of the lower n−m bits of the input gray level data and the state variable data to output a carry bit representative of carry-over of the sum, and a pseudo gray level data calculator generating the pseudo gray level data based on the input gray level data and the carry bit.

Abstract: An error diffusing circuit modifies input video data signals representative of the gray levels of 8-bit gradation to output video data signals representative of the gray levels of 6-bit gradation, and an initial value generator produces an initial value for each of the first video data signals on each line of a frame, wherein the initial value generator varies the initial value depending upon the combination of a frame number, a line number and the color so that any pattern is not unintentionally produced on the display panel.

Abstract: In a liquid crystal display device where each unit pixel p arranged on a liquid crystal panel 101A is constituted by a plurality of pixels p1, p2, and p3, the pixels p1, p2, and p3 are divided into sub-pixels p11 and p12, sub-pixels p21, and p22, and sub-pixels p31 and p32, respectively. The liquid crystal display device is provided with driver ICs 201 and 202 for driving the sub-pixels p11, p21, and p31, and the sub-pixels p12, p22, and p32 constituting the pixels so that different gradation-brightness value characteristics may be given. Due to this, multi-gradation display can be performed.

Abstract: A display panel 13 having a plurality of pixels 14 each divided into P (P=3) sub-pixels 15a, 15b and 15c, and a source driver 12 for driving each pixel 14 in accordance with three J (=8)-bit data values corresponding to the sub-pixels 15a, 15b, and 15c, and a signal processing circuit 12 for distributing K(=12)-bit (K>J) input image data as M (M=6) time-shared frame data values and supplying the frame data values to the source driver 12 are arranged. 2K−J (=16) gray levels insufficient due to the difference between the numbers of bits of K-bit input image data and J-bit driving signals of the source driver 12 is realized by combinations of time-shared frame data of (P×M=18) ways performed for the sub-pixels 15a, 15b, and 15c in accordance with the M time-shared frame data values.

Abstract: A liquid crystal display control circuit receives a data enable signal DE in synchronization with per-line based display data from a computer, and thereby controls a liquid crystal display. A gate drive signal outputted from a gate driver 23 is generated according to a vertical clock signal VCK in synchronization with a rise of the signal DE. In order to avoid a variation in the period of charging the pixel electrodes which is caused by a delay in the rise timing of the signal DE and a delay in the signal VCK after the last line, a gate enable signal generation circuit 10 is provided in the liquid crystal display control circuit 1, whereby the extended output of the pulse of the gate drive signal caused by the above-mentioned delays is inhibited. This avoids display inhomogeneity caused by a variation in the data enable signal and the like.

Abstract: A display apparatus is composed of a pseudo gray level data processor generating pseudo gray level data having m bits based on input gray level data having n bits. The pseudo gray level data processor includes a state variable generator generating a state variable data having n−m bits, based on lower n−m bits of the input gray level data, an adder calculating a sum of the lower n−m bits of the input gray level data and the state variable data to output a carry bit representative of carry-over of the sum, and a pseudo gray level data calculator generating the pseudo gray level data based on the input gray level data and the carry bit.