Patents by Inventor Maciej Bajkowski

Maciej Bajkowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit and method for latch bypass
    Patent number: 7362134
    Abstract: A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: April 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Maciej Bajkowski, George P. Hoekstra, Prashant U. Kenkare, Ravindraraj Ramaraju
  • LEVEL SHIFTING CIRCUIT
    Publication number: 20080054980
    Abstract: A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 6, 2008
    Inventors: Maciej Bajkowski, George P. Hoekstra, Hamed Ghassemi
  • Circuit and method for latch bypass
    Publication number: 20070222480
    Abstract: A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.
    Type: Application
    Filed: March 24, 2006
    Publication date: September 27, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Maciej Bajkowski, George Hoekstra, Prashant Kenkare, Ravindraraj Ramaraju