Patents by Inventor Maciej Burel

Maciej Burel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor processing systems with in-situ electrical bias
    Patent number: 11894240
    Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: February 6, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso
  • Semiconductor processing system with in-situ electrical bias and methods thereof
    Patent number: 11837652
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: December 5, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • Semiconductor Processing System with In-Situ Electrical Bias and Methods Thereof
    Publication number: 20220262921
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: David Hurley, Ioan Domsa, lan Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • Semiconductor processing system with in-situ electrical bias and methods thereof
    Patent number: 11335792
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 17, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • SEMICONDUCTOR PROCESSING SYSTEM WITH IN-SITU ELECTRICAL BIAS AND METHODS THEREOF
    Publication number: 20210313444
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 7, 2021
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • SEMICONDUCTOR PROCESSING SYSTEMS WITH IN-SITU ELECTRICAL BIAS
    Publication number: 20210313189
    Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
    Type: Application
    Filed: February 25, 2021
    Publication date: October 7, 2021
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso