Patents by Inventor Maciej Maciejewski

Maciej Maciejewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10691506
    Abstract: Systems and methods for managing locks in a data acquisition system with a distributed data storage are disclosed. In embodiments, a storage node of a data acquisition system with a plurality of storage nodes receives a request for an unprocessed event, where portions of the event data are stored across the plurality of storage nodes. One node of the plurality of nodes holds the lock value for the event. The node receiving the request searches for an event where it stores the lock value that is unlocked. If none is found, the node receiving the request forwards the request to a second node, which repeats the search.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Grzegorz Jereczek, Jakub Radtke, Pawel Makowski, Maciej Maciejewski, Pawel Lebioda, Piotr Pelplinski, Aleksandra Wisz
  • Patent number: 10552319
    Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Grzegorz Jereczek, Pawel Lebioda, Maciej Maciejewski, Pawel Makowski, Piotr Pelplinski, Jakub Radtke, Aleksandra Wisz
  • Publication number: 20190138368
    Abstract: Systems and methods for managing locks in a data acquisition system with a distributed data storage are disclosed. In embodiments, a storage node of a data acquisition system with a plurality of storage nodes receives a request for an unprocessed event, where portions of the event data are stored across the plurality of storage nodes. One node of the plurality of nodes holds the lock value for the event. The node receiving the request searches for an event where it stores the lock value that is unlocked. If none is found, the node receiving the request forwards the request to a second node, which repeats the search.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Grzegorz JERECZEK, Jakub RADTKE, Pawel MAKOWSKI, Maciej MACIEJEWSKI, Pawel LEBIODA, Piotr PELPLINSKI, Aleksandra WISZ
  • Patent number: 10282287
    Abstract: Memory devices and systems having direct access mode (DAM) space allocation across interleaved non-volatile memory (NVM) modules, as well as methods of allocating direct access mode (DAM) space across interleaved non-volatile memory (NVM) modules are disclosed and described.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Wojciech Malikowski, Maciej Maciejewski
  • Publication number: 20190042443
    Abstract: Examples may include techniques to manage data in a data acquisition system including allocating memory in a first stage buffer; storing data received by a data provider into the allocated memory in the first stage buffer; and storing a key identifying the stored data and an address in the first stage buffer for the stored data in an entry in a first keys data structure. Further steps include receiving a request from a filtering unit to get the stored data from the first stage buffer, the request including the key; retrieving the address in the first stage buffer from the entry in the first keys data structure associated with the key; and returning the address in the first stage buffer to the filtering unit.
    Type: Application
    Filed: March 2, 2018
    Publication date: February 7, 2019
    Inventors: Maciej MACIEJEWSKI, Piotr PELPINSKI, Grzegorz JERECZEK, Jakub RADTKE, Wojciech MALIKOWSKI, Pawel MAKOWSKI
  • Publication number: 20190042409
    Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 1, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Grzegorz Jereczek, Pawel Lebioda, Maciej Maciejewski, Pawel Makowski, Piotr Pelplinski, Jakub Radtke, Aleksandra Wisz
  • Publication number: 20170185293
    Abstract: Memory devices and systems having direct access mode (DAM) space allocation across interleaved non-volatile memory (NVM) modules, as well as methods of allocating direct access mode (DAM) space across interleaved non-volatile memory (NVM) modules are disclosed and described.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Applicant: Intel Corporation
    Inventors: Wojciech Malikowski, Maciej Maciejewski