Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

Abstract: A resistive sensor system includes resistive sensor pairs formed of first and second sensors of opposite sensitivity directions to a measured property. Each resistive sensor pair includes one of the first sensors having a first terminal and a second terminal, and one of the second sensors having a third terminal and a fourth terminal. The fourth terminal is coupled to the second terminal of the first sensor. The system further includes multiple noninverting switch elements, each having a noninverting output coupled to the first terminal of one the first sensors, and multiple inverting switch elements, each having an inverting output coupled to the third terminal of one of the second sensors. For each resistive sensor pair, the noninverting and inverting switch elements receive a switch signal for controlling the noninverting and inverting switch elements such that the first and second sensors are biased in opposition to one another.

Abstract: A resistive sensor system includes resistive sensor pairs formed of first and second sensors of opposite sensitivity directions to a measured property. Each resistive sensor pair includes one of the first sensors having a first terminal and a second terminal, and one of the second sensors having a third terminal and a fourth terminal. The fourth terminal is coupled to the second terminal of the first sensor. The system further includes multiple noninverting switch elements, each having a noninverting output coupled to the first terminal of one the first sensors, and multiple inverting switch elements, each having an inverting output coupled to the third terminal of one of the second sensors. For each resistive sensor pair, the noninverting and inverting switch elements receive a switch signal for controlling the noninverting and inverting switch elements such that the first and second sensors are biased in opposition to one another.

Abstract: An integrated circuit includes a load circuit having multiple functional modules, a first voltage regulator configured to provide a supply voltage to the multiple functional modules, and a supply current monitoring circuit including a second voltage regulator and a current monitor, the second voltage regulator being configured to provide a test supply voltage. A switch matrix is interconnected between the first voltage regulator, the supply current monitoring circuit, and the functional modules. Each of the functional modules in successive order is a module under test, and the switch matrix is configured to disconnect the first voltage regulator from the module under test and connect the supply current monitoring circuit to the module under test such that the second voltage regulator provides the test supply voltage to the module under test and the current monitor measures a supply current of the module under test in response to the test supply voltage.