Patents by Inventor Maciej Sosin

Maciej Sosin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9784778
    Abstract: A system for measuring electrical charge, comprising a capacitance detector (110) connected to a charge integrator (120) being an operational amplifier with capacitance (Cf) feedback (130), wherein the input stage (121) of the charge integrator (120) comprises a pair of symmetrically connected complementary JFET transistors (T1, T2), the gates of which are connected to the input of the charge integrator (120), characterized in that an n-type transistor (T1) of the complementary pair of transistors (T1, T2) has its drain connected to a voltage regulating system (122).
    Type: Grant
    Filed: December 14, 2014
    Date of Patent: October 10, 2017
    Assignee: Uniwersytet Jagiellonski
    Inventors: Zbigniew Sosin, Marek Adamczyk, Maciej Sosin, Pawel Lasko
  • Publication number: 20160274159
    Abstract: A system for measuring electrical charge, comprising a capacitance detector (110) connected to a charge integrator (120) being an operational amplifier with capacitance (Cf) feedback (130), wherein the input stage (121) of the charge integrator (120) comprises a pair of symmetrically connected complementary JFET transistors (T1, T2), the gates of which are connected to the input of the charge integrator (120), characterized in that an n-type transistor (T1) of the complementary pair of transistors (T1,T2) has its drain connected to a voltage regulating system (122).
    Type: Application
    Filed: December 14, 2014
    Publication date: September 22, 2016
    Inventors: Zbigniew SOSIN, Marek ADAMCZYK, Maciej SOSIN, Pawel LASKO
  • Patent number: 9103860
    Abstract: A system for measuring electrical charge, comprising a capacitance detector (110) connected to a charge integrator (120) being an operational amplifier with a capacitance feedback (130), in which the input stage (121) of the charge integrator (120) comprises a pair of symmetrically connected JFET-type transistors (T1; T2), having gates connected to the input of the charge integrator (120).
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: August 11, 2015
    Assignee: UNIWERSYTET JAGIELLONSKI
    Inventors: Zbigniew Sosin, Maciej Sosin, Marek Adamczyk
  • Publication number: 20140049269
    Abstract: A system for measuring electrical charge, comprising a capacitance detector (110) connected to a charge integrator (120) being an operational amplifier with a capacitance feedback (130), in which the input stage (121) of the charge integrator (120) comprises a pair of symmetrically connected JFET-type transistors (T1; T2), having gates connected to the input of the charge integrator (120).
    Type: Application
    Filed: February 22, 2012
    Publication date: February 20, 2014
    Applicant: UNIWERSYTET JAGIELLONSKI
    Inventors: Zbigniew Sosin, Maciej Sosin, Marek Adamczyk