Abstract: Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described. A combined fixed-point and floating-point vector multiplication circuit may include at least one switch to change the circuit between a first mode and a second mode. In the first mode, the circuit is to multiply mantissas from a same element position of a first floating-point vector and a second floating-point vector to produce a product, shift the products, produce signed representations of the shifted products, add the signed representations of the shifted products to produce a single product, and normalize the single product into a single floating-point resultant. In the second mode, the circuit is to multiply values from a same element position of a first integer vector and a second integer vector to produce a corresponding product, and add each corresponding product to produce a single integer resultant.

Abstract: Execution of computing workloads by a fleet of multiple Kubernetes clusters in a distributed computing environment in managed by determining on which of a plurality of managed clusters to place the workloads, by tracking and matching resource needs of the workloads with cluster resource capacities and availability. Common workloads related to multi-tenancy across subsets of the fleet of clusters can be duplicated, thereby enabling standardization of clusters and prevention of redundant manifests across software repositories. Workloads may be placed according to different policies, including placing them on an ordered set of target clusters and, according to the ordered set, prioritizing the workloads in the ordered set, or on statically, pre-determined clusters. Clusters may also be cloned and, on demand, new clusters may be brought up and idle clusters may be shut down. The start of workloads may also be triggered from a failed cluster to a different functional cluster.

Abstract: Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described.

Abstract: A method comprising storing a plurality of entries, each entry of the plurality of entries associated with a portion of a range of input values, each entry of the plurality of entries comprising a set of coefficients defining a power series approximation; selecting first entry of the plurality of entries based on a determination that a floating point input value is within a portion of the range of input values that is associated with the first entry; and calculating an output value by evaluating the power series approximation defined by the set of coefficients of the first entry at the floating point input value.

Abstract: Systems, apparatuses and methods may provide for technology that in response to an identification that one or more hardware units are to execute on a first type of data format, decomposes a first original floating point number to a plurality of first segmented floating point numbers that are to be equivalent to the first original floating point number. The technology may further in response to the identification, decompose a second original floating point number to a plurality of second segmented floating point numbers that are to be equivalent to the second original floating point number. The technology may further execute a multiplication operation on the first and second segmented floating point numbers to multiply the first segmented floating point numbers with the second segmented floating point numbers.

Abstract: Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described.

Abstract: A method comprising storing a plurality of entries, each entry of the plurality of entries associated with a portion of a range of input values, each entry of the plurality of entries comprising a set of coefficients defining a power series approximation; selecting first entry of the plurality of entries based on a determination that a floating point input value is within a portion of the range of input values that is associated with the first entry; and calculating an output value by evaluating the power series approximation defined by the set of coefficients of the first entry at the floating point input value.

Abstract: Systems, apparatuses and methods may provide for technology that in response to an identification that one or more hardware units are to execute on a first type of data format, decomposes a first original floating point number to a plurality of first segmented floating point numbers that are to be equivalent to the first original floating point number. The technology may further in response to the identification, decompose a second original floating point number to a plurality of second segmented floating point numbers that are to be equivalent to the second original floating point number. The technology may further execute a multiplication operation on the first and second segmented floating point numbers to multiply the first segmented floating point numbers with the second segmented floating point numbers.

Abstract: Systems, methods, and apparatuses for broadcasting a selected data element and performing an operation in response to a single instruction are described. For example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, at least two packed data source operand identifiers, a packed data destination operand identifier, and an immediate, and execution circuitry to execute the decoded instruction to: broadcast a packed data element from the identified first packed data source operand, wherein the packed data element position to be broadcast is selected based on a value of the immediate, perform operations according to the opcode on the broadcasted packed data element from the identified first packed data source operand and packed data elements of the identified second packed data source operand is described.