Patents by Inventor Maciej Wiatr

Maciej Wiatr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170330970
    Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 16, 2017
    Inventors: Arkadiusz Malinowski, Chung Foong Tan, Nicolas Sassiat, Maciej Wiatr
  • Patent number: 9812573
    Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: November 7, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Arkadiusz Malinowski, Chung Foong Tan, Nicolas Sassiat, Maciej Wiatr
  • Patent number: 9627409
    Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: April 18, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Peter Moll, Andrei Sidelnicov, Maciej Wiatr
  • Patent number: 9515155
    Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Roman Boschke, Stefan Flachowsky, Maciej Wiatr, Christian Schippel
  • Publication number: 20160300856
    Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.
    Type: Application
    Filed: December 29, 2015
    Publication date: October 13, 2016
    Inventors: Hans-Peter Moll, Andrei Sidelnicov, Maciej Wiatr
  • Publication number: 20160071947
    Abstract: A method disclosed herein includes providing a substrate including a semiconductor material. A first area of the substrate is recessed relative to a second area of the substrate, and an active region of a first transistor is formed in the recessed area. An active region of a second transistor is formed in the second area of the substrate. First and second dummy gate structures are formed over the active regions of the first transistor and the second transistor, respectively. At least a portion of the first and second dummy gate structures is replaced with at least a portion of a gate structure of the first transistor and the second transistor, respectively. The gate structure of the first transistor includes a ferroelectric material, and the gate structure of the second transistor does not include a ferroelectric material.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 10, 2016
    Inventors: Maciej Wiatr, Stefan Flachowsky
  • Patent number: 9263582
    Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Maciej Wiatr
  • Patent number: 9153534
    Abstract: Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-?/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-? dielectric layer on the STI region, forming a metal gate on the high-? dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: October 6, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Andreas Kurz, Maciej Wiatr
  • Publication number: 20150200270
    Abstract: When forming semiconductor devices comprising high performance or low-power field effect transistors, the threshold voltage of the transistors is adjusted by the halo implantation and the source and drain regions are defined by a single implantation step. Thus, the number of process steps is reduced, whereas the electrical characteristics, such as leakage level, and performance of the transistors are maintained compared to conventional transistors.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 16, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Hermann Sachse, Maciej Wiatr
  • Publication number: 20150179753
    Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: Globalfoundries Inc.
    Inventors: Roman Boschke, Stefan Flachowsky, Maciej Wiatr, Christian Schippel
  • Publication number: 20150054083
    Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.
    Type: Application
    Filed: September 30, 2014
    Publication date: February 26, 2015
    Inventors: Stephan Kronholz, Maciej Wiatr
  • Publication number: 20150034953
    Abstract: Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-?/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-? dielectric layer on the STI region, forming a metal gate on the high-? dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventors: Andreas KURZ, Maciej WIATR
  • Patent number: 8939765
    Abstract: In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Peter Javorka, Maciej Wiatr, Roman Boschke, Christian Krueger
  • Patent number: 8884379
    Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: November 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Maciej Wiatr
  • Patent number: 8836047
    Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: September 16, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8778772
    Abstract: Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: July 15, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chung Foong Tan, Maciej Wiatr, Peter Javorka, Falong Zhou
  • Patent number: 8748275
    Abstract: In sophisticated semiconductor devices, a semiconductor alloy, such as a threshold adjusting semiconductor material in the form of silicon/germanium, may be provided in an early manufacturing stage selectively in certain active regions, wherein a pronounced degree of recessing and material loss, in particular in isolation regions, may be avoided by providing a protective material layer selectively above the isolation regions. For example, in some illustrative embodiments, a silicon material may be selectively deposited on the isolation regions.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: June 10, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Juergen Thees, Stephan Kronholz, Maciej Wiatr
  • Patent number: 8722486
    Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Maciej Wiatr, Roman Boschke, Peter Javorka
  • Patent number: 8722481
    Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8709902
    Abstract: In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any additional process steps by using a sacrificial spacer element as an etch mask and as an implantation mask for incorporating the drain and source dopant species for deep drain and source areas for one type of transistor. On the other hand, the usual main spacer may be used for the incorporation of the deep drain and source regions of the other type of transistor.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: April 29, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Kerstin Ruttloff, Maciej Wiatr, Stefan Flachowsky