Abstract: A mechanism for controlling asynchronous clock domains to perform synchronous operations is provided. With the mechanism, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation a manufacturing test sequence, debug operation, or the like.

Abstract: A multi-use eFuse macro is presented. A device includes multiplexers and selection logic that allow eFuse latches to store auxiliary data in addition to programming electronic fuses. The multiplexers and selection logic are coupled to the inputs and outputs of the eFuse latches, and are controlled by a processing unit or an external tester. When a tester wishes to program or update an eFuse element (electronic fuses), the multiplexers and selection logic are configured for “eFuse” mode, which allows an eFuse controller to provide program data and control data to the eFuse latches which, in turn, program the eFuse element. When the device requires additional storage, the multiplexers and selection logic are configured for “auxiliary data” mode, which allows a processing unit to store and retrieve data in the eFuse latches.

Abstract: A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.

Abstract: A system and method for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

Abstract: A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.

Abstract: A system and method for testing an integrated circuit device with asynchronous clocks or dissimilar design methodologies are provided. With the system and method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

Abstract: A data processing system including an arrangement for modifying the usual priority arbitration of an input/output channel controller (IOCC) used in granting direct memory access (DMA) service among contending peripheral devices sharing a common peripheral bus. The IOCC includes logic for conditioning the established priority arbitration scheme based upon the data status of the data buffers. If the higher priority requesting device requires a data transfer between the system memory and the IOCC prior to performing an operation directly between the IOCC and the peripheral device, the priority will instead be granted to a lower priority peripheral device that does not require a system memory access operation.

Abstract: A frequency multiplier circuit including a circuit element to receive an input signal having a first frequency which is provided to a phase shifting circuit element to provide an intermediate signal resembling the input signal except shifted in phase. This intermediate signal is provided to a logic element which combines the intermediate frequency with the input signal to produce an output signal having a second frequency which is a multiple of the first frequency.