Patents by Inventor Mack Wayne Riley
Mack Wayne Riley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9336105Abstract: Provided is an apparatus that includes a processor comprising a plurality of processing cores and a corresponding plurality of LBIST modules, each LBIST module corresponding to one of the plurality of processing cores; a MISR read out connection, comprising a compare value register, a plurality of MISR registers equal in number to the plurality of cores, each MISR register corresponding to one of the plurality of processing cores and a corresponding plurality of XOR logic gates, each XOR logic gate coupled to the compare value register and a corresponding one of the MISR registers and configured to signal whether or not the event the compare value register and the corresponding MISR register match and logic, stored and executed on the processor, for transmitting the signals generated by the plurality of XOR logic gates.Type: GrantFiled: September 30, 2010Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventor: Mack Wayne Riley
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Publication number: 20120084603Abstract: Provided is an apparatus that includes a processor comprising a plurality of processing cores and a corresponding plurality of LBIST modules, each LBIST module corresponding to one of the plurality of processing cores; a MISR read out connection, comprising a compare value register, a plurality of MISR registers equal in number to the plurality of cores, each MISR register corresponding to one of the plurality of processing cores and a corresponding plurality of XOR logic gates, each XOR logic gate coupled to the compare value register and a corresponding one of the MISR registers and configured to signal whether or not the event the compare value register and the corresponding MISR register match and logic, stored and executed on the processor, for transmitting the signals generated by the plurality of XOR logic gates.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Mack Wayne Riley
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Patent number: 7831006Abstract: An apparatus is provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.Type: GrantFiled: June 4, 2008Date of Patent: November 9, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Mack Wayne Riley, Michael Fan Wang
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Patent number: 7809974Abstract: A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counter. The first divider outputs a second clock signal at a second clock frequency. A second divider is interposed between the clocking circuit and the counter. A processor is coupled to an output of the first divider.Type: GrantFiled: January 16, 2008Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Mack Wayne Riley, Michael Fan Wang
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Patent number: 7702944Abstract: The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.Type: GrantFiled: January 12, 2009Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Nathan Chelstrom, Mack Wayne Riley, Michael Fan Wang, Stephen Douglas Weitzel
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Patent number: 7698608Abstract: A mechanism is provided for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy data from each subsequent test in the same bank of eFuses, a latch on a scan chain is used that holds the programming information for each eFuse. This latch allows for programming only a portion of eFuses during each stage of testing. Moreover, the data programmed in the eFuses can be sensed and read as part of a scan chain. Thus, it can be easily determined what portions of the bank of eFuses have already been programmed by a previous stage of testing and where to start programming the next set of data into the bank of eFuses. As a result, the single bank of eFuses stores multiple sets of data from a plurality of test stages.Type: GrantFiled: December 14, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventor: Mack Wayne Riley
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Patent number: 7656237Abstract: An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.Type: GrantFiled: December 2, 2004Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: Mack Wayne Riley, Daniel Lawrence Stasiak, Michael Fan Wang, Stephen Douglas Weitzel
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Patent number: 7620126Abstract: A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.Type: GrantFiled: September 27, 2005Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: David William Boerstler, Matthew E. Fernsler, Eskinder Hailu, Jieming Qi, Mack Wayne Riley
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Patent number: 7590194Abstract: An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.Type: GrantFiled: September 27, 2005Date of Patent: September 15, 2009Assignee: International Business Machines CorporationInventors: David William Boerstler, Matthew E. Fernsler, Eskinder Hailu, Jieming Qi, Mack Wayne Riley
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Publication number: 20090222251Abstract: A design structure for a integrated circuit interfacing system may be embodied in a machine readable medium for designing, manufacturing or testing a integrated circuit. In one embodiment, the design structure specifies an integrated circuit that includes multiple interfaces. The design structure may specify that each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. The design structure may also specify a bridge circuit on the integrated circuit that switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.Type: ApplicationFiled: December 31, 2008Publication date: September 3, 2009Applicant: International Business Machines CorporationInventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack Wayne Riley, Shoji Sawamura, Iwao Takiguchi
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Patent number: 7546504Abstract: A system and method for advanced logic built-in self test with selection of scan channels is present. An LBIST controller loads scan patterns into a device's scan channels through sequential or interleaved loading techniques in order to minimize instantaneous power requirements. During interleave loading, the LBIST controller loads a scan bit into a first scan chain, then into a second scan chain, etc. until one bit is loaded into each scan chain. The LBIST controller then returns to load another scan bit into the first scan channel, then the second scan channel, etc. During sequential loading, the LBIST controller loads an entire scan pattern into a first scan chain (one bit per clock cycle). Once the first scan pattern is loaded, the LBIST controller proceeds to load subsequent scan patterns into corresponding scan chains on a one bit per scan channel per clock cycle basis.Type: GrantFiled: August 11, 2006Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Mack Wayne Riley, Michael Fan Wang
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Publication number: 20090121747Abstract: A system and method for maintaining circuit delay characteristics during power management mode. The method for maintaining circuit delay characteristics during power management mode continually toggles the clock distribution circuits at a frequency sufficiently low that it does not significantly impact chip power dissipation. The clock frequency used to toggle the clock distribution circuits is high enough to minimize the asymmetrical stress on the clock buffer transistors so that both P and N device characteristics equally change over time.Type: ApplicationFiled: November 12, 2007Publication date: May 14, 2009Inventors: Sang Hoo Dhong, Peter Harm Hofstee, Mack Wayne Riley, James Douglas Warnock, Stephen Douglas Weitzel
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Publication number: 20090119552Abstract: The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.Type: ApplicationFiled: January 12, 2009Publication date: May 7, 2009Inventors: Nathan Chelstrom, Mack Wayne Riley, Michael Fan Wang, Stephen Douglas Weitzel
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Patent number: 7516350Abstract: The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.Type: GrantFiled: September 9, 2004Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: Nathan Chelstrom, Mack Wayne Riley, Michael Fan Wang, Stephen Douglas Weitzel
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Publication number: 20090058503Abstract: An eFuse system that includes a mechanism that bridges banks of eFuses and allows the banks of eFuses to be placed any distance from each other. The bridging of the eFuse banks is transparent to compression and encode programming algorithm and hardware decode mechanisms. Thus, by using the mechanism for bridging gaps between eFuse banks, an eFuse subsystem with several banks distributed on an integrated circuit chip appears to be a single large eFuse bank to the encode/decode mechanisms of the integrated circuit. Additionally, with this mechanism, eFuse banks can be easily added or deleted.Type: ApplicationFiled: August 30, 2007Publication date: March 5, 2009Inventors: Michael Joseph Genden, Mack Wayne Riley
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Patent number: 7484153Abstract: Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed to determine whether any of the processor cores is malfunctioning. If none of the processor cores malfunctions, the processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor is fully functional. If one or more processor cores malfunctions, these processor cores are isolated and the remaining processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor operates properly with reduced functionality.Type: GrantFiled: December 6, 2005Date of Patent: January 27, 2009Assignees: Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Naoki Kiryu, Mack Wayne Riley, Nathan Paul Chelstrom
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Publication number: 20080272820Abstract: A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.Type: ApplicationFiled: June 4, 2008Publication date: November 6, 2008Applicant: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Mack Wayne Riley, Michael Fan Wang
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Method to reduce transient current swings during mode transitions of high frequency/high power chips
Patent number: 7430264Abstract: A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.Type: GrantFiled: November 4, 2004Date of Patent: September 30, 2008Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Mack Wayne Riley, Michael Fan Wang -
Publication number: 20080147901Abstract: In one embodiment, the disclosed methodology and apparatus involves an integrated circuit that includes multiple interfaces. Each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. A bridge circuit on the integrated circuit switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.Type: ApplicationFiled: October 31, 2006Publication date: June 19, 2008Applicant: IBM CorporationInventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack Wayne Riley, Shoji Sawamura, Iwao Takiguchi
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Publication number: 20080133957Abstract: The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.Type: ApplicationFiled: January 16, 2008Publication date: June 5, 2008Inventors: David William Boerstler, Eskinder Hailu, Mack Wayne Riley, Michael Fan Wang