Abstract: A control circuit for a voltage regulator includes a divider coupled to the regulated output voltage to generate a divided voltage having a value that is a fraction of the regulated output voltage, an ADC responsive to the divided voltage to generate a feedback control signal, a digital compensator responsive to the feedback control signal and to a feedforward control signal scaled by a feedforward gain value to generate a compensator signal, and a pulse width modulator responsive to the compensator signal to generate a voltage control signal to control a switch of the voltage regulator. The digital compensator includes a register configured to store a value indicative of the input voltage and a feedforward gain unit configured to generate the feedforward gain value in response to the value indicative of the input voltage. In embodiments, the feedforward gain value is generated in response to the square of the value indicative of the input voltage.

Abstract: A control circuit for a voltage regulator includes a divider coupled to the regulated output voltage to generate a divided voltage having a value that is a fraction of the regulated output voltage, an ADC responsive to the divided voltage to generate a feedback control signal, a digital compensator responsive to the feedback control signal and to a feedforward control signal scaled by a feedforward gain value to generate a compensator signal, and a pulse width modulator responsive to the compensator signal to generate a voltage control signal to control a switch of the voltage regulator. The digital compensator includes a register configured to store a value indicative of the input voltage and a feedforward gain unit configured to generate the feedforward gain value in response to the value indicative of the input voltage. In embodiments, the feedforward gain value is generated in response to the square of the value indicative of the input voltage.

Abstract: A tunable fractional phase locked loop (PLL) (hereinafter “tunable PLL”) is described herein and includes a controller configured to tune the tunable PLL to a range of frequencies corresponding to a frequency of the input clock signal. The tunable PLL includes a phase detector configured to receive an input clock signal and a feedback signal, a voltage controller oscillator (VCO) configured to receive the error signal from said phase detector and in response thereto to generate a VCO clock signal, a controller configured to generate a dithered division ratio having an average value corresponding to a ratio of a number of edges of the VCO clock signal generated in a cycle of the input clock signal, and a feedback module configured to generates a feedback signal to tune the PLL such that the PLL operates in the range of input frequencies of the input clock signal.

Abstract: A control circuit for a voltage regulator includes a digital compensator having adaptive compensation to permit operation over different operating conditions. The digital compensator includes a gain parameter that is inversely proportional to the input voltage and is independent of the switching frequency. In embodiments, the voltage regulator has a crossover frequency established by at least one pole and at least one zero and the corner frequency of the converter output filter has a first fixed, predetermined relationship with respect to the switching frequency, a second fixed, predetermined relationship with respect to the crossover frequency, and a third fixed, predetermined relationship with respect to the at least one pole and at least one zero.

Abstract: A control circuit for a voltage regulator includes a digital compensator having adaptive compensation to permit operation over different operating conditions. The digital compensator includes a gain parameter that is inversely proportional to the input voltage and is independent of the switching frequency. In embodiments, the voltage regulator has a crossover frequency established by at least one pole and at least one zero and the corner frequency of the converter output filter has a first fixed, predetermined relationship with respect to the switching frequency, a second fixed, predetermined relationship with respect to the crossover frequency, and a third fixed, predetermined relationship with respect to the at least one pole and at least one zero.