Patents by Inventor Madan Krishnappa
Madan Krishnappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934219Abstract: An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.Type: GrantFiled: March 29, 2022Date of Patent: March 19, 2024Assignee: QUALCOMM INCORPORATEDInventors: Arvind Jain, Divya Gangadharan, Muhammad Nasir, Hong Dai, Madan Krishnappa
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Publication number: 20240087662Abstract: A system for repairing a random access memory may include serial test interface logic, fuse-sense logic, a repair data register chain, and multiplexing logic. The repair data register chain may include serially interconnected data registers configured to shift data through the repair data register chain. Each data register of the repair data register chain may have a data output configured to be coupled to a repair information input of the random access memory. The multiplexing logic may be configured to provide a soft-repair mode and a hard-repair mode. When the soft-repair mode is selected, the multiplexing logic may be configured to receive soft-repair data provided by the serial test interface logic into the data registers. When the hard-repair mode is selected, the multiplexing logic may be configured to receive the data provided by the fuse-sense logic into the data registers.Type: ApplicationFiled: September 14, 2022Publication date: March 14, 2024Inventors: HONG DAI, Amir BOROVIETZKY, Arvind JAIN, Massine BITAM, Madan KRISHNAPPA
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Publication number: 20230315141Abstract: An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Arvind JAIN, Divya GANGADHARAN, Muhammad NASIR, Hong DAI, Madan KRISHNAPPA
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Publication number: 20230299050Abstract: Stacked circuits are configured to facilitate post-stacking testing. According to one example, a stacked circuit may include a first die electrically coupled to a second die through a plurality of interconnects. The first die may include a test input interface configured to receive test data signals and a source test clock signal, a test output interface configured to convey test responses, a first test signal path, at least one first die-to-die output interface configured to convey to the second die the test data signals and a low-latency clock signal received from a low-latency clock path between the test input interface and the at least one first die-to-die output interface, and at least one first die-to-die input interface configured to receive test responses and the clock signal from the second die. Other aspects, embodiments, and features are also included.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Inventors: Kunal Jain MANGILAL, Madan KRISHNAPPA
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Publication number: 20230267096Abstract: The reliability of a data communication link may be analyzed and otherwise maintained by collecting a two-dimensional array representing a functional data eye, and using a convolutional neural network to determine a score of the functional data eye. The determined score may be compared with a threshold, and an action may be initiated based on the result of the comparison.Type: ApplicationFiled: April 23, 2021Publication date: August 24, 2023Inventors: Uttkarsh WARDHAN, Vishal GHORPADE, Sanku MUKHERJEE, Madan KRISHNAPPA, Sanath Sreekana BANGALORE, Pankhuri AGARWAL, Santanu PATTANAYAK
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Publication number: 20220138613Abstract: A method performed by a machine learning system includes generating a set of reward values based on a set of parameter values selected by a machine learning system, each reward value of the set of reward values corresponding to a parameter value of the set of parameter values programmed at a device. The method also includes determining a reward function for maximizing a reward corresponding to a set of parameters of the device based on the set of reward values. The method further includes tuning a parameter of the set of parameters based on the reward function.Type: ApplicationFiled: October 29, 2020Publication date: May 5, 2022Inventors: Uttkarsh WARDHAN, Vishal GHORPADE, Sanku MUKHERJEE, Madan KRISHNAPPA, Pankhuri AGARWAL, Sanath Sreekanta BANGALORE, Santanu PATTANAYAK
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Patent number: 11250197Abstract: Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.Type: GrantFiled: October 26, 2020Date of Patent: February 15, 2022Assignee: QUALCOMM IncorporatedInventors: Vinod Kumar Lakshmipathi, Venugopal Sanaka, Babu Suriamoorthy, Madan Krishnappa, Pavan Kumar Patibanda
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Publication number: 20200293415Abstract: Certain aspects of the present disclosure generally relate to memory training. An example method generally includes assigning each of a plurality of data channels of a memory device to at least one processor, performing memory tests, in parallel, on the plurality of data channels by at least in part performing read and write operations on at least two or more of the plurality of data channels in parallel using the at least one processor, and determining a setting for one or more memory interface parameters associated with the memory device relative to a data eye for each of the plurality of data channels determined based on the memory tests.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Inventors: Sanku MUKHERJEE, Uttkarsh WARDHAN, Madan KRISHNAPPA
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Patent number: 10114443Abstract: A thermal controller for managing thermal energy of a multi-core processor is provided. The cores include a first core processing a load and remaining cores. The thermal controller is configured to determine that a temperature of the first core is greater than a first threshold, determine a temperature of a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold, and determine whether the temperature of the second core is greater than or less than a second threshold. The thermal controller is configured to transfer at least a portion of the load of the first core to the second core in response to determining that the temperature of the first core is greater than the first threshold and based on whether the temperature of the second core is greater than or less than the second threshold.Type: GrantFiled: February 23, 2017Date of Patent: October 30, 2018Assignee: QUALCOMM IncorporatedInventors: Rajat Mittal, Madan Krishnappa, Rajit Chandra, Mohammad Tamjidi
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Patent number: 9933827Abstract: Various aspects of a power management approach for a system-on-a-chip (SoC) is disclosed herein. In one aspect, the approach includes implementing a power profile for supplying power to a plurality of subsystems on a shared power bus in the SoC. The power profile includes at least one adjustable parameter for controlling the supplied power during an active use state. The approach further includes detecting a power profile change trigger; modifying the power profile based on the power profile change trigger; and adjusting the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level.Type: GrantFiled: February 19, 2013Date of Patent: April 3, 2018Assignee: QUALCOMM IncorporatedInventors: Ajay Cheriyan, Rajesh Joshi, Madan Krishnappa
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Patent number: 9846612Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.Type: GrantFiled: August 11, 2015Date of Patent: December 19, 2017Assignee: QUALCOMM IncorporatedInventors: Madan Krishnappa, Chinh Tran, Li Zhang, Alan Young, William Bainbridge, Bohuslav Rychlik
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Publication number: 20170160785Abstract: A thermal controller for managing thermal energy of a multi-core processor is provided. The cores include a first core processing a load and remaining cores. The thermal controller is configured to determine that a temperature of the first core is greater than a first threshold, determine a temperature of a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold, and determine whether the temperature of the second core is greater than or less than a second threshold. The thermal controller is configured to transfer at least a portion of the load of the first core to the second core in response to determining that the temperature of the first core is greater than the first threshold and based on whether the temperature of the second core is greater than or less than the second threshold.Type: ApplicationFiled: February 23, 2017Publication date: June 8, 2017Inventors: Rajat MITTAL, Madan KRISHNAPPA, Rajit CHANDRA, Mohammad TAMJIDI
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Patent number: 9612636Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.Type: GrantFiled: September 25, 2014Date of Patent: April 4, 2017Assignee: QUALCOMM IncorporatedInventors: Matthew Levi Severson, Shih-Hsin Jason Hu, Dipti Ranjan Pal, Madan Krishnappa, Jeffrey Gemar, Noman Ahmed, Mohammad Tamjidi, Mark Kempfert
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Patent number: 9582052Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a UE. The UE has a processor including a plurality of cores. The plurality of cores includes a first core and remaining cores. The UE determines a temperature of the first core of the plurality of cores. The first core processes a load. The UE determines that the temperature of the first core is greater than a first threshold. The UE determines that the temperature of the first core is not greater than a second threshold. The second threshold is greater than the first threshold. The UE transfers at least a portion of the load of the first core to a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold.Type: GrantFiled: March 31, 2015Date of Patent: February 28, 2017Assignee: QUALCOMM IncorporatedInventors: Rajat Mittal, Madan Krishnappa, Rajit Chandra, Mohammad Tamjidi
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Publication number: 20170046219Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.Type: ApplicationFiled: August 11, 2015Publication date: February 16, 2017Inventors: MADAN KRISHNAPPA, CHINH TRAN, LI ZHANG, ALAN YOUNG, WILLIAM BAINBRIDGE, Bohuslav RYCHLIK
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Publication number: 20170046218Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.Type: ApplicationFiled: August 11, 2015Publication date: February 16, 2017Inventors: MADAN KRISHNAPPA, CHINH TRAN, LI ZHANG, ALAN YOUNG, WILLIAM BAINBRIDGE
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Publication number: 20160124476Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a UE. The UE has a processor including a plurality of cores. The plurality of cores includes a first core and remaining cores. The UE determines a temperature of the first core of the plurality of cores. The first core processes a load. The UE determines that the temperature of the first core is greater than a first threshold. The UE determines that the temperature of the first core is not greater than a second threshold. The second threshold is greater than the first threshold. The UE transfers at least a portion of the load of the first core to a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold.Type: ApplicationFiled: March 31, 2015Publication date: May 5, 2016Inventors: Rajat MITTAL, Madan KRISHNAPPA, Rajit CHANDRA, Mohammad TAMJIDI
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Publication number: 20160091939Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.Type: ApplicationFiled: September 25, 2014Publication date: March 31, 2016Inventors: Matthew Levi SEVERSON, Shih-Hsin Jason HU, Dipti Ranjan PAL, Madan KRISHNAPPA, Jeffrey GEMAR, Noman AHMED, Mohammad TAMJIDI, Mark KEMPFERT
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Patent number: 8984308Abstract: A particular method includes, prior to issuing a recommendation by an adaptive voltage scaling (AVS) system, performing a first iteration of an AVS operation to sample characteristics of a semiconductor device to determine a first adjustment recommendation. The method further includes performing at least one additional iteration of the AVS operation to determine at least one additional adjustment iteration. When a threshold number of consecutive adjustment recommendations are consistent, the method includes issuing the recommendation by the AVS system.Type: GrantFiled: December 3, 2012Date of Patent: March 17, 2015Assignee: QUALCOMM IncorporatedInventor: Madan Krishnappa
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Patent number: 8975954Abstract: An integrated circuit (IC) includes an adaptive voltage scaling (AVS) controller configured to control a voltage supplied to a portion of the IC and at least one sensor configured to sense at least one state of the IC and to provide an output signal indicative of the at least one sensed state to the AVS controller, the IC having a first setting and a second setting, the AVS controller being configured to use the output signal to control the voltage in the first setting and the AVS controller being configured to control the voltage independently of the output signal in the second setting. Also a method of performing AVS is provided.Type: GrantFiled: January 8, 2013Date of Patent: March 10, 2015Assignee: QUALCOMM IncorporatedInventors: Madan Krishnappa, Stephen Simmonds, Parag Arun Agashe, Sajjad Pagarkar, Ashwin Rabindranath, Sagar Digwalekar