Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.

Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.

Abstract: Aspects of the present disclosure are directed to detecting and powering external circuits via a common port. As may be implemented in accordance with one or more embodiments, an accessory detection circuit detects a type of an external circuit based upon a pull-down resistance at an interface port (e.g., where each accessory type provides a discernable pull-down resistance). Power switching circuitry couples power between the interface port and an internal power-based circuit, and operates in an open condition when the accessory detection circuit is active. An adaptive biasing circuit sets a voltage across the power switching circuitry to about zero, based on a voltage level provided on the interface port, thereby mitigating changes in the pull-down resistance due to current leakage. Once the type of external circuit is identified, the power switching circuitry couples power between the external circuit and the internal circuit.

Abstract: A protocol can specifie a power-sourcing voltage range that indicates power sourcing capabilities. Additional power sourcing capabilities can be communicated using voltage variations within the power-sourcing voltage range. A power-sourcing device can provide power to an external power-sinking device over a wired connection containing a plurality of wires. A voltage control circuit can be configured to drive a voltage over a wire of the plurality of wires. Processing circuitry can communicate, using the voltage control circuit, first power-sourcing capabilities to the external power-sinking device by setting the voltage over the wire to a value within the power-sourcing voltage range. The processing circuitry can also communicate, using the voltage control circuit, the additional power sourcing capabilities of the power-sourcing device using voltage variations on the wire, the voltage variations maintaining voltage on the wire within the power-sourcing voltage range.

Abstract: Aspects of the present disclosure are directed to detecting and powering external circuits via a common port. As may be implemented in accordance with one or more embodiments, an accessory detection circuit detects a type of an external circuit based upon a pull-down resistance at an interface port (e.g., where each accessory type provides a discernable pull-down resistance). Power switching circuitry couples power between the interface port and an internal power-based circuit, and operates in an open condition when the accessory detection circuit is active. An adaptive biasing circuit sets a voltage across the power switching circuitry to about zero, based on a voltage level provided on the interface port, thereby mitigating changes in the pull-down resistance due to current leakage. Once the type of external circuit is identified, the power switching circuity couples power between the external circuit and the internal circuit.

Abstract: One or more characteristics of devices are ascertained in accordance with one or more aspects of the disclosure. As may be consistent with one or more embodiments, the attachment of an external circuit to an input port is detected based on a resistance value presented by the external circuit. A resistance range that includes the resistance value presented at the input port is determined, in response to detecting the attachment, by dynamically coupling one or more of a plurality of resistor-based circuits relative to the input port. A signal presented by the external circuit on the input port is coded based on the determined resistance range, using one or more of the resistor-based circuits, and the code is used to identify a type of the external circuit. These aspects can provide for the communication of power and data with a variety of different types of external circuits.

Abstract: Various aspects of the disclosure are directed to methods and apparatuses involving providing a clock signal. As consistent with one or more embodiments herein, a sawtooth waveform signal is generated in a manner that facilitates low power operation. In some implementations, the sawtooth waveform signal is generated using an oscillator that operates without necessarily employing R-C circuits and/or without rail-to-rail voltage supply, such as via a nonlinear oscillator. The sawtooth waveform signal is used to generate a trapezoidal waveform signal, and a clock signal is generated using the trapeziodal waveform signal.

Abstract: A voltage regulator circuit and a method for operating the voltage regulator circuit are described. In one embodiment, a voltage regulator circuit includes an input terminal to receive an input signal from a power interface, an output terminal to output an output signal using the input signal, an output voltage monitor circuit configured to compare the voltage of the output signal with a predetermined voltage threshold, and a current limit circuit configured to limit current flowing on a path from the input terminal to the output terminal to a transient current limit level. The transient current limit level is lower than a predefined current limit threshold of the power interface. Other embodiments are also described.

Abstract: Aspects are directed to low dropout regulation. In accordance with one or more embodiments, an apparatus includes a charge pump that generates an output using a reference voltage, a low dropout (LDO) regulator circuit, current-limit and a voltage-limit circuit. The LDO circuit includes an amplifier powered by the charge pump and that provides an LDO voltage output. The voltage-limit circuit includes a transistor coupled between a voltage supply line and the LDO regulator circuit and a gate driven by the charge pump. The voltage-limit circuit limits voltage coupled between the voltage supply line and the LDO regulator circuit based upon the output of the charge pump, such as by coupling the voltage at the voltage supply line via source/drain connection of the transistor under low-voltage conditions, and providing a limited voltage to the LDO regulator circuit under high voltage conditions on the voltage supply line.

Abstract: Various aspects of the disclosure are directed to methods and apparatuses involving providing a clock signal. As consistent with one or more embodiments herein, a sawtooth waveform signal is generated in a manner that facilitates low power operation. In some implementations, the sawtooth waveform signal is generated using an oscillator that operates without necessarily employing R-C circuits and/or without rail-to-rail voltage supply, such as via a nonlinear oscillator. The sawtooth waveform signal is used to generate a trapezoidal waveform signal, and a clock signal is generated using the trapeziodal waveform signal.

Abstract: Low voltage circuits are protected from high voltage/current conditions, as may be implemented in accordance with one or more example embodiments. An additional/secondary shunt circuit/switch is implemented to shunt additional current as supply voltage steps or otherwise increases. In some implementations, the secondary shunt circuit includes a transistor having its drain coupled to its gate via a large capacitance that operates to maintain the gate voltage at about a constant level. This operates to facilitate the draining of additional current, and maintaining a low bandgap voltage supply level.

Abstract: Low voltage circuits are protected from high voltage/current conditions, as may be implemented in accordance with one or more example embodiments. An additional/secondary shunt circuit/switch is implemented to shunt additional current as supply voltage steps or otherwise increases. In some implementations, the secondary shunt circuit includes a transistor having its drain coupled to its gate via a large capacitance that operates to maintain the gate voltage at about a constant level. This operates to facilitate the draining of additional current, and maintaining a low bandgap voltage supply level.

Abstract: Aspects are directed to low dropout regulation. In accordance with one or more embodiments, an apparatus includes a charge pump that generates an output using a reference voltage, a low dropout (LDO) regulator circuit, current-limit and a voltage-limit circuit. The LDO circuit includes an amplifier powered by the charge pump and that provides an LDO voltage output. The voltage-limit circuit includes a transistor coupled between a voltage supply line and the LDO regulator circuit and a gate driven by the charge pump. The voltage-limit circuit limits voltage coupled between the voltage supply line and the LDO regulator circuit based upon the output of the charge pump, such as by coupling the voltage at the voltage supply line via source/drain connection of the transistor under low-voltage conditions, and by providing a limited voltage to the LDO regulator circuit under high voltage conditions on the voltage supply line.

Abstract: A voltage regulator circuit and a method for operating the voltage regulator circuit are described. In one embodiment, a voltage regulator circuit includes an input terminal to receive an input signal from a power interface, an output terminal to output an output signal using the input signal, an output voltage monitor circuit configured to compare the voltage of the output signal with a predetermined voltage threshold, and a current limit circuit configured to limit current flowing on a path from the input terminal to the output terminal to a transient current limit level. The transient current limit level is lower than a predefined current limit threshold of the power interface. Other embodiments are also described.

Abstract: A low-drop out (LDO) regulator circuit is provided having a gate of a pass transistor coupled to an output of an operational transconductance amplifier, the LDO regulator exhibiting a non-dominant pole at an output of the LDO. A dynamic zero-compensation circuit is coupled in parallel to the pass transistor. A compensation control circuit is coupled and configured to adjust a frequency, at which a zero is generated, and cause the generated zero to track with the non-dominant pole.

Abstract: A low-drop out (LDO) regulator circuit is provided having a gate of a pass transistor coupled to an output of an operational transconductance amplifier, the LDO regulator exhibiting a non-dominant pole at an output of the LDO. A dynamic zero-compensation circuit is coupled in parallel to the pass transistor. A compensation control circuit is coupled and configured to adjust a frequency, at which a zero is generated, and cause the generated zero to track with the non-dominant pole.