Abstract: A wide band-gap semiconductor layer structure is provided that comprises a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided in an upper surface of the wide band-gap semiconductor layer structure. Second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure to simultaneously form well regions underneath the source regions and trench shielding regions underneath the trenches, the well regions and the trench shielding regions each having a second conductivity type.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a gate trench formed in an upper surface thereof, a gate finger in the gate trench, a supplemental dielectric layer on an upper surface of the gate finger and vertically overlaps the gate trench, and a gate connector on an upper surface of the supplemental dielectric layer and on an upper surface of the gate finger.

Abstract: A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.

Abstract: A power semiconductor device includes a semiconductor structure having a first side, a second side, and a drift region of a first conductivity type therebetween, and implanted regions of a second conductivity type in the semiconductor structure adjacent the first side of the semiconductor structure. The implanted regions include first portions of a first material and second portions of a second material, with the second portions positioned between the first portions and the second side. The second material has an atomic weight that is lighter than that of the first material. Related fabrication methods are also discussed.

Abstract: A silicon carbide semiconductor device includes a drift layer, a channel layer on the drift layer, the channel layer having a first conductivity type, a trench in the channel layer and a mesa adjacent to the trench, and a gate region within the trench. The gate region has a second conductivity type opposite the first conductivity type, and the gate region includes an epitaxially regrown layer. A method of forming a silicon carbide semiconductor device includes providing a drift layer, forming a channel layer on the drift layer, the channel layer having a first conductivity type, etching the channel layer to form a trench in the channel layer and a mesa adjacent to the trench, and epitaxially regrowing a gate region within the trench, wherein the gate region has a second conductivity type opposite the first conductivity type.

Abstract: Semiconductor devices are provided that comprise a semiconductor layer structure that comprises a drift region having a first conductivity type and a gate junction region having a second conductivity type, and a gate trench in the semiconductor layer structure. At least a portion of the gate junction region that is on a sidewall of the gate trench may have a tapered shape in a cross-sectional view.

Abstract: A gate-controlled semiconductor device comprises a semiconductor layer structure and a gate trench in the semiconductor layer structure. The semiconductor layer structure comprises a drift region that has a first conductivity type, a trench shield that has a second conductivity type underneath the gate trench, and a support shield that has the second conductivity type extending toward a lower surface of the semiconductor layer structure. The support shield has a peak doping concentration at a first depth from the upper surface of the semiconductor layer structure. A lowermost portion of the trench shield is at a second depth from the upper surface of the semiconductor layer structure that is less than the first depth, and a thickness of the trench shield is less than the first depth minus the second depth.

Abstract: A gate-controlled semiconductor device comprises a semiconductor layer structure and a gate trench in the semiconductor layer structure. The semiconductor layer structure comprises a drift region that has a first conductivity type, a trench shield that has a second conductivity type underneath the gate trench, and a support shield that has the second conductivity type extending toward a lower surface of the semiconductor layer structure. The support shield has a peak doping concentration at a first depth from the upper surface of the semiconductor layer structure. A lowermost portion of the trench shield is at a second depth from the upper surface of the semiconductor layer structure that is less than the first depth, and a thickness of the trench shield is less than the first depth minus the second depth.

Abstract: A semiconductor device includes a semiconductor layer having an active region and a gate contact region adjacent the active region, a plurality of alternating mesa stripes and trenches in the active region, a gate contact pad on the semiconductor layer, and an under-gate mesa in the gate contact region beneath the gate contact pad. The semiconductor device may have a saw street at an outer periphery of the semiconductor layer, wherein a top surface of the saw street is at a same height above the substrate as top surfaces of the plurality of mesa stripes.

Abstract: JFETs are provided that comprise a wide bandgap semiconductor layer structure comprising an active region and a termination region. The termination region comprises a plurality of termination structures. A first major surface of the semiconductor layer structure in the active region comprises a plurality of spaced-apart mesas and the first major surface of the semiconductor layer structure in the termination region is a planar surface.

Abstract: A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.

Abstract: A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that comprises a drift region, a plurality of well regions having a second conductivity type on the drift region, and a plurality of source regions having a first conductivity type on the well regions.

Abstract: A semiconductor device comprises a semiconductor layer structure that comprises a drift region having a first conductivity type and a trench shielding region having a second conductivity type, and a gate trench extending in a longitudinal direction in the semiconductor layer structure. The trench shielding region extends in the longitudinal direction underneath the gate trench, and at least a portion of the trench shielding region comprises sidewalls that angle inwardly with increasing distance from the gate trench.

Abstract: A power semiconductor device includes a semiconductor structure comprising an active region, a plurality of gates that extend in a first direction in or on the active region of the semiconductor structure, at least one integrated polysilicon device in or on the semiconductor structure adjacent the active region, and a gate connector electrically connecting the plurality of gates. The gate connector is in or on the semiconductor structure between the at least one integrated polysilicon device and the plurality of gates. The at least one integrated polysilicon device is electrically isolated from the gate connector devoid of an inter-polysilicon dielectric layer therebetween. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes an active region comprising a plurality of alternating trenches and mesas in an epitaxial layer, the plurality of alternating trenches and mesas extending in a first direction, and an edge termination region adjacent the active region and including a first edge termination region and a second edge termination region. The edge termination region includes first and second guard ring trenches adjacent the active region that are separated by a termination mesa that extends in the first direction in the first edge termination region and extends in a second direction, perpendicular to the first direction, in the second edge termination region. The termination mesa has a first width in the first edge termination region and the termination mesa has a second width in the second edge termination region that is different from the first width.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface therebetween. A bottom shielding structure of a second conductivity type is provided under the bottom surface of the gate trench. First and second support shielding structures of the second conductivity type extend into the drift region on opposing sides of the gate trench and are spaced apart from the sidewalls thereof. A material composition, distance of extension into the drift region relative to a surface of the semiconductor layer structure, and/or dopant concentration of the bottom shielding structure may be different from that of the first and second support shielding structures. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device comprises a semiconductor layer structure that has a gate trench therein and a source metallization layer on the semiconductor layer structure. The semiconductor layer structure comprises a drift region having a first conductivity type, a trench shield that has a second conductivity type, the trench shield positioned underneath the gate trench, and a trench shield connection pattern that has the second conductivity type, the trench shield connection pattern electrically connecting the trench shield to the source metallization layer, where the trench shield connection pattern extends deeper into the semiconductor layer structure than the trench shield.

Abstract: A semiconductor device includes a device active region comprising a first well, at least a portion of the first well being part of a first metal-oxide-semiconductor field-effect transistor (MOSFET), and a sensor region comprising a second well, at least a portion of the second well being part of a second MOSFET configured to mirror a current in the first MOSFET. A distance between an outer edge of the second well and an inner edge of the first well is constant or the distance decreases approaching one or more vertices of the second well.

Abstract: A semiconductor device comprises a semiconductor layer structure comprising a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, and a first JFET region having the first conductivity type, and a gate trench extending into the semiconductor layer structure. An upper surface of the first JFET region is positioned below the gate trench. A first conductivity dopant concentration of the first JFET region exceeds a first conductivity dopant concentration of the drift region.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a junction field-effect transistor (JFET) region of a first conductivity type, a well region of a second conductivity type on the JFET region, a source region of the first conductivity type on the well region and a plurality of support shields of the second conductivity type. The support shields are spaced apart from one another in a first direction parallel to an upper surface of the semiconductor layer structure and extend through the source region, the well region and the JFET region. The semiconductor device further includes a trenched gate structure formed in the semiconductor layer structure between a pair of adjacent support shields. Edges of at least two of the JFET region, the well region and the source region are aligned in a second direction perpendicular to the first direction.