Abstract: A semiconductor device comprises a silicon carbide based semiconductor layer structure that comprises a drift region having a first conductivity type and an implanted region having a second conductivity type on the drift region. First and second gate trench sections extend into the semiconductor layer structure. A first maximum depth into the semiconductor layer structure of a first portion of the implanted region that is between the first gate trench section and the second gate trench section is different than a second maximum depth into the semiconductor layer structure of a second portion of the implanted region that extends downwardly underneath the first gate trench section.

Abstract: Semiconductor devices are provided that comprise a semiconductor layer structure that comprises a drift region having a first conductivity type, a channel region having a second conductivity type, and a source region having the first conductivity type. A gate trench extends into an upper surface of the semiconductor layer structure. The channel region horizontally overlaps both the gate trench and the source region.

Abstract: A semiconductor device comprises a silicon carbide based semiconductor layer structure that includes a drift layer having a first conductivity type, a gate trench that extends to a first depth into an upper surface of the semiconductor layer structure, a gate electrode in the gate trench, a support shield trench that extends to a second depth into the upper surface of the semiconductor layer structure, where the second depth is less than the first depth, and a source metallization layer on the upper surface of the semiconductor layer structure and extending into the support shield trench.

Abstract: A semiconductor device comprises a silicon carbide based semiconductor layer structure and a first gate trench extending into an upper portion of the semiconductor layer structure. The semiconductor layer structure comprises a drift region having a first conductivity type, a well layer having a second conductivity type, and a support shield having the second conductivity type. A width of a first segment of the support shield that is deeper in the semiconductor layer structure than the well layer and less deep in the semiconductor layer structure than a bottom of the first gate trench decreases with increasing distance from the well region.

Abstract: A method of forming a semiconductor device includes forming mesa stripe structure on a semiconductor substrate, the mesa stripe structure including a plurality of alternating trenches and mesa stripes, forming a dielectric spacer on the mesa stripe structure, and forming an etch mask on a portion of the mesa stripe structure. The etch mask covers at least a portion of a first mesa stripe of the plurality of mesa stripes. The dielectric spacer is etched to expose surfaces of the mesa stripes other than the portion of the first mesa stripe that is covered by the etch mask. The etch mask is removed, and a metal layer is formed on the mesa stripe structure. The metal layer forms metal contacts to the exposed surfaces of the mesa stripes. Related semiconductor devices are also disclosed.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a semiconductor structure. The semiconductor device includes a gate finger in a gate trench in the semiconductor structure. The gate trench extends a length in the semiconductor structure. The gate trench has a first portion having a first width and a second portion having a second width. The second width is different than the first width.

Abstract: A semiconductor device comprises a silicon carbide based semiconductor layer structure that comprises an active region. A gate trench is provided in an upper portion of the semiconductor layer structure, the gate trench having a first rounded lower corner and a second rounded lower corner. A gate electrode is provided in the gate trench. Within the active region, an upper surface of the gate electrode is below or coplanar with an upper surface of the semiconductor layer structure.

Abstract: A semiconductor device includes a semiconductor layer structure having a drift region of a first conductivity type and a well region of a second conductivity type above the drift region. A gate is provided on the semiconductor layer structure adjacent the well region. A buried shielding structure of the second conductivity type is provided under the well region and separated from the well region by a portion of the drift region. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type above the drift region, a gate on the semiconductor layer structure adjacent the well region, and a contact shielding structure of the second conductivity type that vertically extends from the well region into the drift region, and discontinuously extends in one or more lateral directions. Related devices and fabrication methods are also discussed.

Abstract: A method of forming a semiconductor device comprises forming a first mask that includes a longitudinally-extending first opening that has a first width on a semiconductor layer structure. A spacer is formed on sidewalls of the first mask that are exposed by the first opening to form a second mask, where the first and second masks comprise a mask structure that has a longitudinally-extending second opening that has a second width that is smaller than the first width. Dopants are implanted through the second opening to form an implanted region in the semiconductor layer structure. The spacer is at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure underneath the third opening.

Abstract: A method of forming a semiconductor device includes etching a semiconductor layer to form a plurality of mesa stripes in the semiconductor layer. The plurality of mesa stripes extend in a first direction and include mesa sidewalls that extend in the first direction and mesa surfaces at opposite ends of the mesa stripes. An additional mesa region is formed at an end of at least one of the mesa stripes. The additional mesa region is electrically insulated from the at least one of the mesa stripes. A semiconductor device structure includes a plurality of mesa stripes that extend in a first direction and include mesa sidewalls that extend in the first direction and mesa end surfaces at opposite ends of the mesa stripes. An additional mesa region that is electrically insulated from the at least one of the mesa stripes is at an end of at least one of the mesa stripes.

Abstract: A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a gate trench formed in an upper surface thereof, a gate finger in the gate trench, a supplemental dielectric layer on an upper surface of the gate finger and vertically overlaps the gate trench, and a gate connector on an upper surface of the supplemental dielectric layer and on an upper surface of the gate finger.

Abstract: A wide band-gap semiconductor layer structure is provided that comprises a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided in an upper surface of the wide band-gap semiconductor layer structure. Second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure to simultaneously form well regions underneath the source regions and trench shielding regions underneath the trenches, the well regions and the trench shielding regions each having a second conductivity type.

Abstract: A semiconductor device includes a device region and an on-chip sensor region, such as an on-chip current sensor region. The semiconductor device further includes a transition region formed between the device region and the sensor region. A gate contact extends across the transition region. A conductive segment may be formed on the gate contact in the transition region to reduce a resistivity of the material used to form the gate contact. Additionally or alternatively, an isolation region may be formed under the gate contact between a first isolated well region in the device region and a second isolated well region in the sensor region. The isolation region isolates the first isolated well region from the second isolated well region to prevent current in the device region from propagating into the sensor region.

Abstract: A power transistor device includes a drift layer having a first conductivity type and a mesa on the drift layer. The mesa includes a channel region on the drift layer, a source layer on the channel region and a gate region in the mesa adjacent the channel region. The channel region and the source layer have the first conductivity type, and the gate region has a second conductivity type opposite the first conductivity type. The channel region includes a deep conduction region and a shallow conduction region between the deep conduction region and the gate region. The deep conduction region has a first doping concentration, and the shallow conduction region has a second doping concentration that is greater than the first doping concentration.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface therebetween. A bottom shielding structure of a second conductivity type is provided under the bottom surface of the gate trench. First and second support shielding structures of the second conductivity type extend into the drift region on opposing sides of the gate trench and are spaced apart from the sidewalls thereof. A material composition, distance of extension into the drift region relative to a surface of the semiconductor layer structure, and/or dopant concentration of the bottom shielding structure may be different from that of the first and second support shielding structures. Related devices and fabrication methods are also discussed.

Abstract: A silicon carbide (SiC) metal oxide semiconductor (MOS) power device is disclosed which includes an SiC drain semiconductor region, an SiC drift semiconductor region coupled to the SiC drain semiconductor region, an SiC base semiconductor region coupled to the SiC drift semiconductor region, an SiC source semiconductor region coupled to the SiC base semiconductor region, a source electrode coupled to the SiC source semiconductor region, a drain electrode coupled to the SiC drain semiconductor region, a gate electrode, wherein voltage of the gate electrode with respect to the SiC base semiconductor region is less than or equal to about 12 V and thickness of the dielectric material is such that the electric field in the dielectric material is about 4 MV/cm when said gate voltage is about 12 V.

Abstract: A metal-oxide-semiconductor (MOS) power device includes a drain semiconductor region, a drift semiconductor region coupled to the drain semiconductor region, a base semiconductor region coupled to the drift semiconductor region and isolated by the drift semiconductor region from the drain semiconductor region, a source semiconductor region coupled to the base semiconductor region, a source electrode, a drain electrode, a gate electrode provided adjacent at least a portion of but isolated from the drift semiconductor region by a dielectric material, wherein the dielectric material has a thickness between 1 nm and 30 nm multiplied by a correction factor defined as a ratio of dielectric permittivity of the dielectric material and the permittivity of silicon dioxide, and wherein the device is configured to withstand greater than 100 V between the drain electrode and the source electrode when substantially no current is flowing through the drain electrode.