Abstract: A reconfigurable datapath (13b), which may be alternatively configured for various debug modes. These modes include a breakpoint mode (20), counter mode (30a-30c), DMA mode (40), and PSA mode (50). Each configuration uses one or more of two bitcell units: a register bitcell unit (60) and a comparator bitcell unit (70). The inputs and interconnections of these bitcell units (60, 70) determine the configuration, and hence the mode, for which they are to be used.

Abstract: A method of initializing a CPU (14) to run emulation code from a debugger (11). Emulation logic (13) associated with the CPU (14) has a finite state machine (13b) with three modes: a reset mode in which no requests from said debugger or said CPU are serviced, a normal mode in which requests from said debugger are given priority, and a start-up mode in which only requests from said debugger are serviced. For initialization, the finite state machine (13b) is placed in reset mode and held in reset while the start-up mode is requested. When the reset mode is released the start-up mode is immediately serviced. This permits an initialization state to be cleanly applied to the CPU (14).