Patents by Inventor Madhavi Gopal Valluri

Madhavi Gopal Valluri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8245084
    Abstract: A subset of a workload, which includes a total set of dynamic instructions, is identified to use as a trace. Processor unit hardware executes the entire workload in real-time using a particular dataset. The processor unit hardware includes at least one microprocessor and at least one cache. The real-time execution of the workload is monitored to obtain information about how the processor unit hardware executes the workload when the workload is executed using the particular dataset to form actual performance information. Multiple different subsets of the workload are generated. The execution of each one of the subsets by the processor unit hardware is compared with the actual performance information. A result of the comparison is used to select one of the plurality of different subsets that most closely represents the execution of the entire workload using the particular dataset to use as a trace.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Wen-Tzer Thomas Chen, Venkat Rajeev Indukuru, Pattabi Michael Seshadri, Madhavi Gopal Valluri
  • Patent number: 7904870
    Abstract: A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Wen-Tzer Thomas Chen, Venkat Rajeev Indukuru, Pattabi Michael Seshadri, Madhavi Gopal Valluri
  • Publication number: 20090182994
    Abstract: A method, apparatus, and computer-usable program code in a computer system for identifying a subset of a workload, which includes a total set of dynamic instructions, to use as a trace. Processor unit hardware executes the entire workload in real-time using a particular dataset. The processor unit hardware includes at least one microprocessor and at least one cache. The real-time execution of the workload is monitored to obtain information about how the processor unit hardware executes the workload when the workload is executed using the particular dataset to form actual performance information. Multiple different subsets of the workload are generated. The execution of each one of the subsets by the processor unit hardware is compared with the actual performance information. A result of the comparison is used to select one of the plurality of different subsets that roost closely represents the execution of the entire workload using the particular dataset to use as a trace.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 16, 2009
    Inventors: Robert H. Bell, JR., Wen-Tzer Thomas Chen, Venkat Rajeev Indukuru, Pattabi Michael Seshadri, Madhavi Gopal Valluri