Abstract: The invention can include at least one storage cell having a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type. A storage cell can also include at least a first source/drain region and a second source/drain region separated from one another by the channel region. A control gate structure, comprising a semiconductor layer doped to the first conductivity type can be formed over a substrate surface. The control gate structure can be in contact with the channel region. Such a storage cell can be more compact and/or provide longer data retention times than conventional storage cells, such as many conventional dynamic random access memory (DRAM) type cells.

Abstract: An image sensing device can include one or more image sensing cells. Each image sensing cell can have a charge store element formed from a semiconductor material doped to a first conductivity type. The charge store element can be in contact with a channel region formed from a semiconductor material doped to a second conductivity type. The charge store element can have one or more surfaces for exposure to an image source. Each image sensing cell can also include a charge electrode formed from a semiconductor material doped to the first conductivity type that is separated from the charge store element by a semiconductor material doped to the second conductivity type. In addition, one or more current detection electrodes can be included in each image sensing cell. A current detection electrode can pass a current flowing through the channel region in a read operation. Such an image sensing cell can be compact in size and/or have a large image sensing area.

Abstract: The invention can include at least one storage cell having a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type. A storage cell can also include at least a first source/drain region and a second source/drain region separated from one another by the channel region. A control gate structure, comprising a semiconductor layer doped to the first conductivity type can be formed over a substrate surface. The control gate structure can be in contact with the channel region. Such a storage cell can be more compact and/or provide longer data retention times than conventional storage cells, such as many conventional dynamic random access memory (DRAM) type cells.

Abstract: An integrated circuit device can include a plurality of field effect transistors (FETs) having channel depths no greater than a first depth, and at least a first switch junction FET (JFET) having a source coupled to a signal transmission input node, a drain coupled to a signal transmission output node, and a gate. The first switch JFET has a channel depth greater than the first depth. Switch JFETs can enable low resistance configurable switch paths to be created for interconnecting different portions of a same integrated circuit device.