Patents by Inventor Madhu S. Athreya

Madhu S. Athreya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9800781
    Abstract: Technologies are provided in embodiments for receiving an indication of an image processing service request, retrieve environmental information indicative of an environmental condition of an apparatus, retrieving operational information indicative of an operating condition of the apparatus, determining image processing software configuration information based, at least in part, on the image processing service, the environmental information, and the operational information, and causing configuration of at least one image processing software module based, at least in part, on the image processing software configuration information.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventors: Sheethal Bhat, Madhu S. Athreya, Yuh-Lin E. Chang
  • Publication number: 20140267811
    Abstract: Technologies are provided in embodiments for receiving an indication of an image processing service request, retrieve environmental information indicative of an environmental condition of an apparatus, retrieving operational information indicative of an operating condition of the apparatus, determining image processing software configuration information based, at least in part, on the image processing service, the environmental information, and the operational information, and causing configuration of at least one image processing software module based, at least in part, on the image processing software configuration information.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Sheethal Bhat, Madhu S. Athreya, Yuh-Lin E. Chang
  • Publication number: 20130002901
    Abstract: Methods and apparatus relating to fine grained power gating of camera image processing are described. In an embodiment, an Image Signal Processor (ISP) includes a first partition to receive and store image sensor data in a memory during a first time period. The ISP also includes a second partition to process the stored image sensor data during a second time period that follows the first time period. The second partition is entered into a low power consumption state during the first time period. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Inventor: Madhu S. Athreya
  • Publication number: 20130004071
    Abstract: Methods and apparatus relating to an image signal processor architecture that may be optimized for low-power consumption, processing flexibility, and/or user experience are described. In an embodiment, an image signal processor may be partitioned into a plurality of partitions. Each partition may be capable of entering a lower power consumption state. Also, processing by each partition may be done in various modes to optimize for low-power consumption, processing flexibility, and/or user experience. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Inventors: YUH-LIN E. CHANG, Ravi Kolagotla, Madhu S. Athreya
  • Publication number: 20110317034
    Abstract: In some embodiments, an electronic device comprises a first camera and a second camera, a first buffer to receive a first set of input frames from the first camera and a second buffer to receive a second set of input frames from the second camera, a single image signal processor coupled to the first buffer and the second buffer to process the first set of input frames from the first frame buffer using one or more processing parameters stored in a first memory to generate a first video stream and to process the second set of input frames from the second frame buffer using one or more processing parameters stored in a second memory register to generate a second video stream, and a memory module to store the first video stream and the second video stream.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 29, 2011
    Inventors: MADHU S. ATHREYA, JIANPING ZHOU
  • Patent number: 7496801
    Abstract: A scheme for exposing internal debug values in an in-band means via debug packets that are injected sequentially with normal link traffic on a link and do not interrupt or otherwise interfere with normal operation of the link or related devices. Therefore, this proposal does not require additional pins since the debug values are exposed via debug packets in an in-band means along with normal link traffic and the debug values are exposed synchronously with normal link traffic since the debug packets are injected sequentially.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: February 24, 2009
    Assignee: Intel Corporation
    Inventors: Richard J. Glass, Madhu S. Athreya, Keith A. Drescher, Piyush Desai