Abstract: According to one general aspect, an apparatus may include a branch prediction circuit configured to predict if a branch instruction will be taken or not. The apparatus may include a branch target buffer circuit configured to store a memory segment empty flag that indicates whether or not the memory segment after a target address includes at least one other branch instruction, wherein the memory segment empty flag was created during a commit stage of a prior occurrence of the branch instruction. The branch prediction circuit may be configured to skip over the memory segment if the memory segment empty flag indicates a lack of other branch instruction(s).

Abstract: According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.

Abstract: According to one general aspect, an apparatus may include a main-branch target buffer (BTB). The apparatus may include a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction. The apparatus may include a micro-BTB confidence counter configured to measure a correctness of the prediction information produced by the micro-BTB. The apparatus may further include a micro-BTB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB. The apparatus may also include a micro-BTB enablement circuit configured to enable a usage of the micro-BTB's prediction information, based, at least in part, upon the values of the micro-BTB confidence counter and the micro-BTB misprediction rate counter.

Abstract: According to one general aspect, an apparatus may include a main-branch target buffer (BTB). The apparatus may include a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction. The apparatus may include a micro-BTB confidence counter configured to measure a correctness of the prediction information produced by the micro-BTB. The apparatus may further include a micro-BTB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB. The apparatus may also include a micro-BTB enablement circuit configured to enable a usage of the micro-BTB's prediction information, based, at least in part, upon the values of the micro-BTB confidence counter and the micro-BTB misprediction rate counter.

Abstract: According to one general aspect, an apparatus may include a branch prediction circuit configured to predict if a branch instruction will be taken or not. The apparatus may include a branch target buffer circuit configured to store a memory segment empty flag that indicates whether or not the memory segment after a target address includes at least one other branch instruction, wherein the memory segment empty flag was created during a commit stage of a prior occurrence of the branch instruction. The branch prediction circuit may be configured to skip over the memory segment if the memory segment empty flag indicates a lack of other branch instruction(s).

Abstract: According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.

Abstract: A method includes controlling a power limit of a computing system based on a determined skin temperature of at least one location on an outer surface of a device housing the computing system. A processor includes a processing unit and a power management controller to control a power limit of the processing unit based on a determined skin temperature of at least one location on an outer surface of a device housing the processor.

Abstract: A system includes a functional unit, at least one cache coupled to the functional unit, and a power management unit coupled to the functional unit and the at least one cache, the power management unit configured to trigger the functional unit to initiate prefetching of data to repopulate the at least one cache prior to a predicted exit of the functional unit from an idle mode to an active mode. The system further may include a prediction unit to predict the exit from the idle mode for the functional unit as occurring a predetermined duration from an entry into the idle mode. The prediction unit may determine the predetermined duration based on a history of idle mode durations indicative of durations of previous instances in which the functional unit was in the idle mode.

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

Abstract: Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

Abstract: A system includes a functional unit, at least one cache coupled to the functional unit, and a power management unit coupled to the functional unit and the at least one cache, the power management unit configured to trigger the functional unit to initiate prefetching of data to repopulate the at least one cache prior to a predicted exit of the functional unit from an idle mode to an active mode. The system further may include a prediction unit to predict the exit from the idle mode for the functional unit as occurring a predetermined duration from an entry into the idle mode. The prediction unit may determine the predetermined duration based on a history of idle mode durations indicative of durations of previous instances in which the functional unit was in the idle mode.

Abstract: A method includes adjusting a maximum skin temperature threshold of a device based on a device state, adjusting a power limit for the device based on the adjusted maximum skin temperature threshold, and operating the device based on the adjusted power limit. A processor includes a processing unit and a power management controller to adjust a maximum skin temperature threshold based on a device state and adjust a power limit for the processing unit based on the adjusted maximum skin temperature threshold.

Abstract: A method includes controlling a power limit of a computing system based on a determined skin temperature of at least one location on an outer surface of a device housing the computing system. A processor includes a processing unit and a power management controller to control a power limit of the processing unit based on a determined skin temperature of at least one location on an outer surface of a device housing the processor.

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract: Methods, systems, and media are provided for power management. The power management includes, but is not limited to storing at a computer system a history of canceled entries into a low power state that interrupted a transition of the unit from an active mode to the low power state and disallowing transition of the unit into the low power state when a number of canceled entries indicated by the history of canceled entries exceeds a canceled entry threshold.

Abstract: Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

Abstract: A system and method for efficient management of operating modes within an IC for optimal power and performance targets. On a same die, an SOC includes one or more processing units and a input/output (I/O) controller (IOC). The multiple interfaces within the IOC manage packets and messages according multiple different protocols. The IOC maintains an activity level for each one of the multiple interfaces. This activity level may be based at least on a respective number of transactions executed by a corresponding one of the multiple interfaces. The IOC determines a power estimate for itself based on at least the activity levels. In response to detecting a difference between the power estimate and an assigned I/O power limit for the IOC, a power manager adjusts at least respective power limits for the one or more processing units based on at least the difference.

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.