Abstract: A method for conditioning a photovoltaic module for testing includes setting an effective irradiance of a continuous light source at a target plane, configuring a test photovoltaic module to operate at a substantially maximum power point configuration, positioning the test photovoltaic module adjacent to the target plane, and configuring the test photovoltaic module for testing by removing the light source, cooling the test module to a testing temperature, and reversing the substantially maximum power point configuration.

Abstract: A method for conditioning a photovoltaic module for testing includes setting an effective irradiance of a continuous light source at a target plane, configuring a test photovoltaic module to operate at a substantially maximum power point configuration, positioning the test photovoltaic module adjacent to the target plane, and configuring the test photovoltaic module for testing by removing the light source, cooling the test module to a testing temperature, and reversing the substantially maximum power point configuration.

Abstract: In one aspect of the invention, a semiconductor die includes a plurality of resistive elements operable to receive a voltage differential between at least two of the resistive elements. The semiconductor die also includes a test circuit coupled to at least three tap points along the resistive elements. The test circuit is operable to measure a voltage at at least two of the tap points. A difference in the voltages between the at least two tap points is proportional to a resistance of the one or more resistive elements between the at least two tap points.

Abstract: In one aspect of the invention, a semiconductor die includes a plurality of resistive elements operable to receive a voltage differential between at least two of the resistive elements. The semiconductor die also includes a test circuit coupled to at least three tap points along the resistive elements. The test circuit is operable to measure a voltage at at least two of the tap points. A difference in the voltages between the at least two tap points is proportional to a resistance of the one or more resistive elements between the at least two tap points.

Abstract: A circuit actively monitors and measures the amount of MOS device degradation due to, for example, the hot electron effect, and makes compensatory adjustments to device voltage levels or clock speed to maintain desired levels of functionality and performance. Monitoring can be done separately for NFET and PFET devices to selectively adjust for different degradation rates between the two. In operation, the monitor circuit compares the performance of a stressed device to a reference device, that is, an unstressed device which has not been degraded by the hot-electron effect. The monitor circuit outputs a signal indicating the amount of device degradation. This signal is used to adjust the supply voltage to that device or to the chip or otherwise compensate for the degradation. The monitor circuit can be formed on-chip or off-chip.