Patents by Inventor Madhuban Kishor

Madhuban Kishor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11476817
    Abstract: An active current source load of a fully differential amplifier which is converted into a transconductance (gm) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is gmp at dc and becomes gmp+(gmngate+gmnsrc) at high frequency which triples the UGB when gmp=gmngate/src.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Saurabh Anmadwar, Dheeraj Shetty, Madhuban Kishor
  • Publication number: 20220085778
    Abstract: An active current source load of a fully differential amplifier which is converted into a transconductance (gm) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is gmp at dc and becomes gmp+(gmngate+gmnsrc) at high frequency which triples the UGB when gmp=gmngate/src.
    Type: Application
    Filed: September 16, 2020
    Publication date: March 17, 2022
    Applicant: Intel Corporation
    Inventors: Saurabh Anmadwar, Dheeraj Shetty, Madhuban Kishor
  • Publication number: 20100231266
    Abstract: The present invention provides a system and a method for driving a differential signal which includes a differential data input, a plurality of switches coupled to a current source for steering current depending on the differential data input, a first differential output and a second differential output and a coupled to at least two of the plurality of switches and a first source follower and a second source follower coupled to the first differential output for controlling output impedance. This architecture prevents the common mode noise reflected from the driver from becoming a differential signal and meets the requirements of the LVDS and SubLVDS standard down till 1.62V. Also this architecture is capable of operating in Gbps range making it a high-speed differential driver with very low power.
    Type: Application
    Filed: March 21, 2007
    Publication date: September 16, 2010
    Applicant: NXP B.V.
    Inventor: Madhuban Kishor